Sikun Li

GPU-based real-time simulation and rendering of unbounded ocean surface

We present a multi-resolution mesh model of the ocean surface based on a straightforward terrain LOD scheme, tiled quad-tree, with that the region of ocean surface can be extended limitlessly and readily adapted for GPU acceleration. We have introduced the concept of wrapped fractal surface (WFS) for generating height field map of the ocean. Through WFS self-mapping, we can create a series of WFS and obtain the height field map at discrete times without repeating tiles. By interpolating the height map at regular intervals we can build an ocean surface continuously and dynamically. This paper also studied shallow ocean waves concerned about affects of seaboard and underwater terrain. Experimental results showed that our approach was effective and would satisfy the requirements of a realistic real-time navigation for large-scale seascape.

Coverage Driven Test Generation Framework for RTL Functional Verification

Functional verification is widely recognized as the bottleneck of the hardware design cycle. The coverage-driven verification approach makes coverage the core engine that drives the whole verification flow, which enables reaching high quality verification in a timely manner. In this paper, we present a coverage driven test generation methodology and a set of tools. We present a novel method for automatic generating simulation vectors from HDL descriptions based on path coverage and constraint solving. We present a novel approach to generate functional vectors based on assertions for RTL design verification. Our approach combines program-slicing based design extraction, word-level SAT and dynamic searching techniques. We also present a coverage analysis method based on VCD file, which only replaying the simulation of the control statements in the HDL description. Experimental results show the efficiency of our methodology.

2D Decomposition Sequential Equivalence Checking of System Level and RTL Descriptions

Symbolic simulation-based approach is viable for the sequential equivalence checking (SEC) of SLM-vs.-RTL. However, it cant avoid the storage explosion introduced by the explosion of the BDD sizes for large designs. For scalability, we introduce two kinds of decomposition techniques: One is the equivalence checking oriented program slicing; the other is the hierarchical insertion of logic cut- points. And a 2D decomposition SEC method of SLM-vs.-RTL is presented. 2D decomposition means decomposition in the space dimension and the time dimension. The verification model is only built for the program slices of a single output variable for each time, which limits the usage of memory. During checking the equivalence of the program slices, the logic cutpoints are inserted to split the verification model of the program slices in the time dimension, which controls the storage explosion further. The promising experimental results demonstrate the benefits brought by our 2D decomposition method.

Procedural terrain detail based on Patch-LOD algorithm

The navigation and rendering of very large-scale terrain are facing a difficult problem that the geometry data and texture data cannot be used directly due to the storage space, computation capacity, and I/O bandwidth. To provide more realistic detail of terrain scene, procedural detail is a good solution. Firstly, this paper introduces a method of procedural geometry based on the terrain tile quad-tree and the Patch-LOD algorithm. Then, the texture generation operator is described and the method of dynamic pre-computation of patch-texture is presented. Finally, the experimental system based on these above ideas and methods has been implemented. The experimental results show that these methods are effective and are appropriate to the development of 3D games and battlefield applications.

A Formal Approach to Verify Parameterized Protocols in Mobile Cyber-Physical Systems

Mobile cyber-physical systems (CPSs) are very hard to verify, because of asynchronous communication and the arbitrary number of components. Verification via model checking typically becomes impracticable due to the state space explosion caused by the system parameters and concurrency. In this paper, we propose a formal approach to verify the safety properties of parameterized protocols in mobile CPS. By using counter abstraction, the protocol is modeled as a Petri net. Then, a novel algorithm, which uses IC3 (the state-of-the-art model checking algorithm) as the back-end engine, is presented to verify the Petri net model. The experimental results show that our new approach can greatly scale the verification capabilities compared favorably against several recently published approaches. In addition to solving the instances fast, our method is significant for its lower memory consumption.

ProDFA: Accelerating Domain Applications with a Coarse-Grained Runtime Reconfigurable Architecture

With the on-chip resources largely increased, modern architectures are much different from traditional ones. The relation between temporal computing and spatial computing is getting more and more intricate. In this paper, we first analyzed and compared the abstract computing models of modern architectures. Then, a runtime reconfigurable architecture called programmable dataflow computing architecture (ProDFA) is proposed. The architecture of ProDFA is sumarized, then the process of how applications are mapped and execute are simply introduced. As a case study, a specific reconfigurable structure for symmetric ciphers is implemented. Performance of several typical symmetric ciphers are evaluated. The experimental results show high performance and efficiency of ProDFA.

A New Application Feature Analysis Approach for System-on-Chip Hardware/Software Partitioning

System-on-Chip is comprehensively applied in the image and signal processing field. With higher demands of customers and increasing complexity of System-on-Chip, System-on-Chip system level design issues become more critical. Hardware/software partitioning is an important step in the system level design. Application feature analysis and early design decision for hardware/software partitioning become a “must”. In this paper, we present a new application feature analysis approach. The approach excavates and utilizes application features including control flow, dataflow, computation, storage, and critical code features. And based on the analysis results, feature model is automatically generated to support hardware/software partitioning. The approach can excavate and utilize application features to improve partitioning algorithms and SoC performance. A case of JPEG codec indicates that this approach supports early design decision and helps to design space exploration in hardware/software partitioning.

Application-driven System-on-Chip system model extraction approach

To cope with increasingly complexity and time-to- market pressure, system-on-chip system modeling is introduced to describe system behavior at the highest abstract level. System modeling helps to separate and cooperate between the steps of system level design. This paper puts forward the application-driven system-on- chip system model extraction approach. The approach extracts application features including control/dataflow, computation/storage and critical tasks features, based on which system models are automatically generated. This approach greatly improves efficiency and correctness of system modeling because it needs not manual work. Moreover, the approach fully excavates and utilizes application features to benefit system level design.

ACRP: Application Customized Reconfigurable Pipeline

Reconfigurable architectures have become popular in recent years in the high performance computing field, because of their reconfigurable characteristic and abundant computing resources. These architectures combine the high performance of ASICs with the flexibility of microprocessors. A novel architecture named Application Customized Reconfigurable Pipeline (ACRP) is proposed for domain-specific applications in this paper. According to analyze and abstract the domain computing character, an application Customized Functional Unit (CFU) is designed to execute the frequent instruction sequence efficiently. The CFU is shared with the hardware pipeline which is composed of some Simple Process Elements (SPEs). The experimental results show that ACRP can exploit the CFU-, pipeline- and data-level parallelism efficiently with the area constraint.

A Novel Collaborative Verification Environment for SoC Co-Verification

We designs and implements a system-on-chip SW/HW co-verification environment SoC-Gen, which collaborates formal verification and simulation techniques for SoC co-verification. This paper first give an overview of SoC-Gen, and then focus on the simulation based verification environment: SoC-CBSHVE, which based on componential design and integration methodology The environment adopts automatic software, hardware and simulation wrappers. Simulator adopts asynchronous parallel algorithm and bus-based communication mechanism. Five data buses support verification components simulation communication. Standard message format and unify simulation interfaces easy SoC components design and verification. Experimental results show that SoC-CBSHVE enables easy debugging, rich portability, and high verification speed, at a low cost for system-on-chip system-level software and hardware co-verification.