Tun Li

Design and implementation of a parallel Verilog simulator: PVSim

Parallel HDL simulation is an efficient method to accelerate the verification process of large complex VLSI system design. This paper presents a parallel Verilog simulator-PVSim, which bases on optimistic asynchronous parallel simulation algorithm and MPI library. A new module-based simulation component mapping method is proposed. And an efficient module-based partition algorithm combined with pre-simulation partition algorithm is adopted. This paper introduces the architecture of PVSim, the Verilog component mapping techniques, the distributed simulation cycle arrangement and the circuit partition algorithm in detail. Experimental results show that PVSim can get promising speedup, as well as distributed workload and communication cost across processors.

An automatic circuit extractor for RTL verification

For RTL verification, we have to separate the control and datapath parts contained in the whole design, and apply different verification techniques for different parts. This paper presents a new circuit extraction method using program slicing technique, and develops an elegant theoretical basis based on program slicing for circuit extraction from Verilog description. The technique can obtain a chaining slice for given signals of interest. Compared with related researches, the main advantages of our method include: it is fine grain; it has no HDL coding style limitation; it is precise and is capable of dealing with various Verilog constructions. The technique has been integrated with a commercial simulation environment and incorporated into a design process. The experimental results on practical designs show the significant benefits of the proposed approach.

The Use of UML Sequence Diagram for System-on-Chip System Level Transaction-based Functional Verification

An important problem faced by system-on-chip transaction-based verification is how to design the complex transaction test sequence. Scenario-based sequence diagram is a good way to capture the system level functional specification. In the paper, we propose a method to support transaction level verification of SoC based on UML sequence diagram. We use UML sequence diagram to capture the communication and collaboration behaviour among IP cores in system-on-chip and build high level specification for transaction level verification. Then these sequence diagrams will be used to guide the generation of transaction test sequence. We develop a component-based transaction verification environment named SoC-CBTVE. In the SoC-CBTVE, based on the method, we verify a typical SoC design. Experimental results show that UML sequence diagram can capture the complex communication behaviour among IP cores in SoC design, and efficiently supports SoC system level functional verification

Translation validation of scheduling in high level synthesis

The growing design-productivity gap has made designers shift toward using high-level synthesis (HLS) techniques to generate register transfer level design from high-level languages. Unfortunately, this translation process is very complex and may introduce bugs into the generated design, which can create a mismatch between what a designer intends and what is actually implemented in the circuit. In this paper, we present an equivalence checking method to validate the result of HLS scheduling against the initial high-level program. Finite state machine with data path (FSMD) models were used to represent designs before and after scheduling. The proposed method uses a bisimulation relation approach to prove equivalence. The automatically established bisimulation relation guarantees that for each execution sequence in the design before scheduling, a related and equivalent execution sequence exists in the design after scheduling and vice versa. Our method provides a unified way to deal with various scheduling optimizations. We have implemented our validation technique and compared it with a state-of-the-art HLS scheduling verification method. The promising results show the effectiveness and efficiency of our method.

Coverage Driven Test Generation Framework for RTL Functional Verification

Functional verification is widely recognized as the bottleneck of the hardware design cycle. The coverage-driven verification approach makes coverage the core engine that drives the whole verification flow, which enables reaching high quality verification in a timely manner. In this paper, we present a coverage driven test generation methodology and a set of tools. We present a novel method for automatic generating simulation vectors from HDL descriptions based on path coverage and constraint solving. We present a novel approach to generate functional vectors based on assertions for RTL design verification. Our approach combines program-slicing based design extraction, word-level SAT and dynamic searching techniques. We also present a coverage analysis method based on VCD file, which only replaying the simulation of the control statements in the HDL description. Experimental results show the efficiency of our methodology.

MA/sup 2/TG: a functional test program generator for microprocessor verification

A novel specification driven and constraints solving based method to automatically generate test programs from simple to complex ones for advanced microprocessors is presented in this paper. Our microprocessor architectural automatic test program generator (MA/sup 2/TG) can produce not only random test programs but also a sequence of instructions for a specific constraint by specifying a user constraints file. The proposed methodology makes three important contributions. First, it simplifies the microprocessor architecture modeling and eases adoption of architecture modification via architecture description language (ADL) specification. Second, it generates test programs for specific constraints utilizing the power of state-to-art constraints solving techniques. Finally, the number of test program for microprocessor verification and the verification time are dramatically reduced. We applied this method on DLX processor to illustrate the usefulness of our approach.

Functional vectors generation for RT-level Verilog descriptions based on path enumeration and constraint logic programming

This paper presents a novel method for automatic functional vectors generation from RT-level HDL descriptions based on path coverage and constraint solving. Compared with existing method, the advantage of this method includes: 1) it avoids generating redundant constraints, which will accelerate the test generation process, 2) it solves the problem of how to propagate the internal values to the primary inputs with decision models, 3) it can handle various HDL description styles, and various styles of designs. Experimental results conduct on several practical designs show that our method can efficiently improve the functional vectors generation process. The prototype system has been applied to verify RTL description of a real 32-bits microprocessor core and complex bugs remained hidden in the RTL descriptions are detected.

Efficient translation validation of high-level synthesis

The growing design-productivity gap has made designers shift toward using high-level synthesis (HLS) techniques to generate register transfer level design from high-level languages like C/C++. Unfortunately, this translation process is very complex and is prone to introduce bug into the generated design, which can create a mismatch between what a designer intends and what is actually implemented in the circuit. In this paper, we present an efficient approach to validate the result of HLS against the initial high-level program using translation validation techniques. We redefined the bisimulation relation and proposed a novel algorithm based on it. When compared with the existing method, the proposed method can dramatically reduce the number of automated theorem prover (ATP) querying, which will in turn improve the time cost in equivalence validation. Our method is suitable for structure-preserving transformations such as carried out by Spark synthesizer. We have implemented our validating technique and compared it with a state-of-the-art translation validation method of HLS. The promising results show the effectiveness and efficiency of our method.

Automatic circuit extractor for HDL description using program slicing

Design extraction and reduction have been extensively used in modern VLSI design process. The extracted and reduced design can be efficiently processed by various applications, such as formal verification, simulation, automatic test pattern generation (ATPG). etc. This paper presents a new circuit extraction method using program slicing technique, and develops an elegant theoretical basis based on program slicing for circuit extraction from Verilog description. The technique can obtain achaining slice for given signals of interest. Compared with related researches, the main advantages of the method include that it is fine grain; it has no hardware description language (HDL) coding style limitation; it is precise and is capable of dealing with various Verilog constructions. The technique has been integrated with a commercial simulation environment and incorporated into a design process. The results of practical designs show the significant benefits of the approach.

Equivalence Checking between SLM and TLM Using Coverage Directed Simulation

The always increasing complexity of digital system makes designers start the design from more abstract System Level Modeling (SLM). However, the SLM arouses a new challenge for verification engineer to guarantee the functional equivalence between SLM specifications and Transaction Level Modeling (TLM) or other lower level implementations. This paper proposes a novel method for equivalence checking between SLM and TLM based on coverage directed simulation. In the proposed method, firstly quality measurements based on both code and functional coverage are used to generate simulation stimuli for SLM. Then the generated stimuli are used to simulate the SLM and TLM designs concurrently. Finally, equivalence checking is carried out based on the simulation results of the selected observing variables. With the proposed method, we can check the equivalence between SLM and TLM designs more efficiently with less simulation cost. The promising experimental results show the efficiency of our method.