Sille Van Landschoot

Test-Driven Development as a Reliable Embedded Software Engineering Practice

Due to embedded co-design considerations, testing embedded software is typically deferred after the integration phase. Contrasting with the current embedded engineering practices, Test-Driven Development (TDD) promotes testing software during its development, even before the target hardware becomes available. Principally, TDD promotes a fast feedback cycle in which a test is written before the implementation. Moreover, each test is added to a test suite, which runs at every step in the TDD cycle. As a consequence, test-driven code is well tested and maintainable. Still, embedded software has some typical properties which impose challenges to apply the TDD cycle. Essentially, uploading software to target is generally too time-consuming to frequently run tests on target. Secondary issues are hardware dependencies and limited resources, such as memory footprint or processing power. In order to deal with these limitations, four methods have been identified and evaluated. Furthermore, a number of relevant design patterns are discussed to apply TDD in an embedded environment.

Calculating Fast Fourier Transform by using parallel software design patterns

Multicore embedded systems introduce new opportunities and challenges. Scaling of computational power is one of the main reasons for a transition to a multicore environment. Parallel design patterns, such as Map Reduce, Task Graph, Thread Pool, Task Parallelism assist to derive a parallel approach for calculating the Fast Fourier Transform. By combining these design patterns, a robust application can be obtained. The key issues for concurrent calculation of a Fast Fourier Transform are determined at a higher level avoiding low-level patch-ups.

Evaluation of a dual-core SMP and AMP architecture based on an embedded case study

Typical telecom applications apply a planar architecture pattern based on the processing requirements of each subsystem. In a symmetric multiprocessing environment all applications share the same hardware resources. However, currently embedded hardware platforms are being designed with asymmetric multiprocessor architectures to improve separation and increase performance of noninterfering tasks. These asymmetric multiprocessor architectures allow different planes to be separated and assign dedicated hardware for each responsibility. While planes are logically separated, some hardware is still shared and creates cross-plane influence effects which will impact the performance of the system. The aim of this report is to evaluate, in an embedded environment, the performance of a typical symmetric multiprocessing architecture compared to its asymmetric multiprocessing variant, applied on a telecom application.

Writing Parallel Embedded Software Effectively

Writing parallel software effectively for embedded systems is not an easy task. We believe a new approach is needed to maximize the performance speed-up. Therefore we propose a layered top-down model for parallel embedded software, based on Our Pattern Language for High-Performance Computing. Several case studies were developed to demonstrate the strength of the model. First, a Fast Fourier Transformation algorithm was parallelized using the top-down model. A speed-up was achieved close to the theoretical maximum. Next, a telecommunication system was migrated from a naive symmetric multiprocessing setup to an asymmetric multiprocessing set-up. Finally, an algorithm that searches for sequences in a list of arcs and lines was implemented in two different ways. The strengths and weaknesses of both parallel implementations are explained.

Algorithm Parallelization Using Software Design Patterns, an Embedded Case Study Approach

Multicore embedded systems introduce new opportunities and challenges. Scaling of computational power is one of the main reasons for transition to a multicore environment. In most cases parallelization of existing algorithms is time consuming and error prone, dealing with low-level constructs. Migrating principles of object-oriented design patterns to parallel embedded software avoids this. We propose a top-down approach for refactoring existing sequential to parallel algorithms in an intuitive way, avoiding the usage of locking mechanisms. We illustrate the approach on the well known Fast Fourier Transformation algorithm. Parallel design patterns, such as Map Reduce, Divide-and-Conquer and Task Parallelism assist to derive a parallel approach for calculating the Fast Fourier Transform. By combining these design patterns, a robust and better performing application is obtained.