Silvian Spiridon

A 40nm wideband direct-conversion transmitter with sub-sampling-based output power, LO feedthrough and I/Q imbalance calibration

In the last decade the amount of digital data generated in connection with digital devices such as cameras, media players and high-definition TVs has seen a significant growth. This requires tuners for home networking such as MoCA with increasingly large bandwidth. Though advanced CMOS technology allows for the design of high-speed circuits and systems that can meet the need for more bandwidth, 40nm feature sizes and beyond introduce new challenges in analog circuit design [1]. Moreover, dependence on environmental conditions of device spread and matching performance with parasitic coupling can drastically reduce the overall system performance.

A 375 mW Multimode DAC-Based Transmitter With 2.2 GHz Signal Bandwidth and In-Band IM3

A 40 nm CMOS digital-to-analog converter (DAC) based multimode transmitter (MMTX) is presented. The transmitter can be operated in either narrow- or wideband applications. It has a maximum 2.2 GHz signal bandwidth and exhibits an in-band IM3 of less than - 58 dBc. The MMTX consists of a current-steering DAC with digital sinc equalization and rolloff compensation. By implementing high-speed, feed-forward pipelined digital logic and a distributed decoder, the DAC sampling rate extends to 5 GHz. A distributed regulator approach ensures preservation of the achieved wideband linearity in noisy embedded SoC environments. The MMTX can deliver up to +11 dBm of output power and exhibits 20 dB of analog power backoff with 1 dB steps and a precision better than ±0.1 dB. The MMTX consumes only 375 mW and occupies 1.65 mm2.

{ 58 dBc in 40 nm CMOS

This paper analyses the typical digital modulation techniques used in todays wireless communications. The paper presents the characteristics of the modulation techniques and determines the figure of merit for each particular modulation: bit error rate (BER) vs. Signal-to- noise ration (SNR). The analysis emphasizes the importance of such figure of merit in the context of software defined radios (SDR).

An Analysis on Digital Modulation Techniques for Software Defined Radio Applications

This paper presents the design, analyses and measurement results of a fast differential variable-gain amplifier (VGA) intended for high-speed data streaming applications such as the IEEE 802.11a wireless LAN. The circuit is a seven stage amplifier that offers a programmable gain in the 0divide84 dB range, in 6 dB steps. Each stage has a programmable gain of either 6 dB or 12 dB. Fully differential low power opamps are used. With an opamp gain-bandwidth product (GBW) of about 200 MHz, the input frequency can go as high as 10 MHz. Offset filtering is possible with a high pass filter with programmable 3 dB frequency. The circuit operates at only 2.5 V, making it an ideal choice for low-power mobile applications. The VGA is fabricated in a 0.13 mum standard analog CMOS technology. It occupies 0.18 mm2 and the typical power dissipation is about 7.5 mW

Low power CMOS fully differential variable-gain amplifier

This paper presents a linearity improvement technique for overcoming signal-dependent induced switching time mismatch in DAC-based transmitters. By dynamically triggering a dummy final retiming stage, the signal-dependent induced pattern for the switching time of the DAC current source cells is broken. The immediate effect is the significant distortion reduction (IM3 improves up to 15 dB), especially for narrowband signals. Thus, the full linearity potential of these transmitters is achieved by an IM3 of -73 dBc at 1 GHz for only 2 MHz tone spacing. With minimal design optimizations, the overall DAC power consumption increase due to the dummy triggering is limited to only 10%. Two latest generation (40 nm and 28 nm) high-speed wide-band DAC-based wireline transmitters have been used as test vehicles for verifying this technique.

A linearity improvement technique for overcoming signal-dependent induced switching time mismatch in DAC-Based transmitters

This paper presents the analyses and design of a very high speed 6 bit digital to analog converter intended for high-speed data streaming applications. The DAC is implemented using current switching technique. For eliminating non-monotonicity thermometric coding is used for the first five MSBs. The circuit has differential current outputs. The output voltage is generated externally by the current that the DAC injects into high precision resistors. The circuit operates at only 1.5 V, making it an ideal choice for low-power mobile applications. The circuit exhibits a third order intermodulation (IM3) of about 37 dBc with a full-scale two tone sinusoidal inputs at 150 MHz and 200 MHz. The DAC is fabricated in a 0.13mum in CMOS technology, it occupies 0.3 mm 2 and dissipates less then 7.5 mW

A 6 bit resolution, 1 gsamples/sec digital to analog converter

This paper presents an analysis on determining the optimal number of gain stages of Variable Gain Amplifiers (VGAs) used in direct conversion CMOS multi-standard wireless receivers embedding analog baseband signal conditioning. In order to facilitate design porting, modern re-configurable wireless receivers are based on a modular architecture for the low frequency part of their analog signal conditioning chain, which includes also the VGA. The analysis constructed in this paper determines the optimal number of VGA stages as the solution of the trade-off between the stage amplifiers power consumption and its linearity performance. Based on the presented analysis it results a VGA embedding 7 stages is able to achieve 84 dB gain range and it represents the best choice with respect to optimizing both the VGA power consumption and its linearity performance.

Determining the optimal number of gain stages of variable gain amplifiers used in multi-standard homodyne wireless receivers

Todays mobile terminals are real multiple media platforms compatible to a rather large number of wireless standards. The ideal candidate for such a mobile terminal radio receiver front-end is the Software Defined Radio Receiver (SDRR). The main challenge the designer must overcome is the SDRR circuit level design optimization, while considering the large amount of information comprised in the envisaged wireless standards. By driving the SDRR design through an initial system level analysis, based on a standard independent systematic methodology, the useful information is structured. Thus, a SDRR design recipe is developed based on the circuit / transistor level designer perspective.

Overcoming the challenges of designing CMOS Software Defined Radio Receivers front-ends embedding analog signal conditioning

The tuned Low Noise Amplifier (LNA) is an attractive solution for applications asking for both low power consumption and low noise figure (NF), such as wireless sensors. This paper presents the CMOS LNA with a tunable resonance frequency analysis focused on noise-linearity-bandwidth trade-offs required for implementing a variable resonance frequency. To change the resonance frequency the MOS capacitor capacitance dependence on the DC gate voltage is used. By employing a MOS capacitor bank, the proposed LNA concept can cover a large frequency band, in a few programmable steps.

CMOS LNA with tunable resonance frequency

A 28 nm CMOS software-defined transceiver (SDTRX) enabling high-speed data (HSD) streaming, including ultra HD TV, within home cable networks is presented. By making efficient use of available cable bandwidth, the SDTRX dynamically handles up to 1024-QAM OFDM-modulated HSD streams. This paper addresses SDTRX system-level design methodology as the key driver in enabling performance optimization for achieving a wide frequency range of operation at lowest power and area consumption. By employing an optimized architecture constructed on available state-of-the-art 28 nm functional building blocks, the monolithic SDTRX consists of a mixer-based harmonic rejection RX with a digital-to-analog converter-based TX and a smart phase-locked loop system. It operates over 0.4–1.7 GHz frequency range while consuming less than 475 mW in half-duplex mode. Moreover, by developing a simple transmitter (TX) to receiver (RX) loopback circuit, the system is enabled to efficiently calibrate TX output power and to remove the need for a dedicated external pin. This low-cost SDTRX is embedded in various 28 nm CMOS multimedia system-on-chip and is, to the authors’ knowledge, the first reported transceiver front-end to enable true HSD streaming within home cable networks.