Stefano Bozzola

A Wideband Receiver for Multi-Gbit/s Communications in 65 nm CMOS

High-rate communications technology leveraging the unlicensed spectrum around 60 GHz is almost ready for deployment with several demonstrations of successful wireless links. One key aspect of the transceiver is the ability to handle analog fractional bandwidths in the order of 20%, challenging for both the linear processing chain and the frequency reference generator. In classical LC loaded stages bandwidth trades with gain making them unsuitable for wide band amplifiers at millimeter-waves where the available device gain is relatively low. In this work, we exploit inter-stage coupling realizing higher order filters where wider bandwidth is achieved at the expense of in-band gain ripple only. The receiver adopts a sliding IF architecture employing an integer-N type-II synthesizer, with a three state phase frequency detector charge pump combination, a switched tuned LC VCO followed by a low power wide range divider chain. By judicious choice of charge pump current and filter components integrated phase noise, critical for signal constellation integrity at high rate, is kept low. This paper inspects the inter-stage coupling technique, providing design formulas, and discusses the design of each receiver block. Experiments performed on 65 nm prototypes provide: 6.5 dB maximum noise figure over >;13 GHz bandwidth, -22.5 dBc integrated phase noise while consuming 84 mW.

A wideband mm-Wave CMOS receiver for Gb/s communications employing interstage coupled resonators

Multi-Gb/s wireless communications, allocated in the unlicensed spectrum around 60GHz, have been the topic of intense research in the recent past and devices are expected to hit the market shortly. Key aspects behind the increasing interest for technology deployment are the feasibility of the radio in scaled CMOS and the successful demonstration of Gb/s transmissions [1]. Despite the fact that several circuit techniques at mm-Waves have been introduced in the public literature, key aspects of the analog processing tailored to the application requirements need to be addressed. Four channels covering 57GHz to 66GHz are specified [2]. Considering spreads due to process variation, an ultra-wide RF bandwidth of more than ∼12GHz has to be covered with fine sensitivity. In order to allow high-end rate transmissions, the phase noise of the reference signal is extremely stringent. Furthermore, low power consumption is key to enabling multiple transceivers on the same chip.

An 11.5% frequency tuning, −184 dBc/Hz noise FOM 54 GHz VCO

This work presents a robust, low area, spectral pure 65 nm VCO for mm-wave applications. The varactor, an inversion mode MOS, takes advantage of the minimum feature provided by the technology to optimize capacitance tuning range and Q. The inductor is a 1 turn spiral. A combination of digital and analog tuning is chosen to lower VCO gain. Prototypes show the following measured results: 11.5% frequency tuning range around 54 GHz, phase noise at 10 MHz of -116 dBc/Hz and -122 dBc/Hz maximum and minimum in band, respectively. Power consumption is 7.2 mW.

A sliding IF receiver for mm-wave WLANs in 65nm CMOS

This paper presents a fully integrated receiver for mm-wave WLANs comprising LNA, RF mixer, quadrature IF mixers, local oscillator plus output stage for characterization, in 65 nm CMOS. The IF frequency set to 1/3 the RF frequency slides according to the received frequency. The architecture choice allows running the quadrature VCO around 20 GHz. A Phase Noise of −115 dBc/Hz @ 10 MHz offset from an equivalent LO at RF carrier is achieved with 36 mW power consumption and 12.5% frequency tuning range. The design of building blocks is discussed in details. Implemented prototypes use low-power digital devices and other measured performances are: 28 dB peak gain, 9 dB noise figure, 5 GHz RF bandwidth, −26 dBm 1-dB compression point, ≫ 60 dB IRR. Total Power consumption is 80 mW from 1.5 V supply.

26.3 An 800MS/S 10b/13b receiver for 10GBASE-T Ethernet in 28nm CMOS

The IEEE 802.3an standard describes full-duplex 10Gb/s Ethernet transmission over four pairs of up to 100m UTP cable. The performance required from the analog front end (AFE) of a 10GBASE-T Ethernet transceiver strongly depends on the length of the cable connected to it. Maximum-length cables require the highest performance, and hence, determine the worst-case power dissipation of the transceiver. In practice, however, the vast majority of cable lengths used are below 30m. For these shorter cables, the standard specifies the transmitted power level to be lowered, inherently leading to a reduction in power consumption of the transmitter (TX). In most designs, the power consumption of the receiver (RX), unfortunately, does not benefit from the shorter cable lengths [1,2]. This paper presents a power-efficient 13b RX, implemented in 28nm CMOS. By switching to a 10b mode for short cables, 143mW is saved in the AFE for one complete Ethernet port, comprising four receivers. In addition, to further reduce power, the RX heavily relies on calibrations.

A 60GHz receiver with 13GHz bandwidth for Gbit/s wireless links in 65nm CMOS

This paper presents a wide-band fully integrated receiver for Gbit/s connectivity at mm-waves comprising LNA, RF mixer, quadrature IF mixers, local oscillator (LO), in 65 nm CMOS. The architecture choice is key to meet LO requirements at low power dissipation. We have selected a sliding IF architecture, where the IF frequency, set to 1/3 the RF frequency, slides according to the received frequency. The VCO at 2/3 the RF frequency provides the reference for the first down-conversion and drives two injection locked dividers delivering LO signals for quadrature IF mixing. A Phase Noise of -115 dBc/Hz @ 10 MHz offset from an equivalent 60GHz carrier is achieved with 12.6% frequency tuning range. Coupled interstage resonators are introduced in the low-noise amplifier to extend considerably the gain bandwidth product, leading to more than 13GHz bandwidth with 26dB LNA gain. Selection of the architecture and design of building blocks are discussed in details. Realized prototypes of the receiver show a conversion gain of 35dB, 13GHz RF input bandwidth and noise figure below 6dB with a power dissipation, including LO generation, of 75mW only.

A 28 nm, 475 mW, and 0.4–1.7 GHz Embedded Transceiver Front-End Enabling High-Speed Data Streaming Within Home Cable Networks

A 28 nm CMOS software-defined transceiver (SDTRX) enabling high-speed data (HSD) streaming, including ultra HD TV, within home cable networks is presented. By making efficient use of available cable bandwidth, the SDTRX dynamically handles up to 1024-QAM OFDM-modulated HSD streams. This paper addresses SDTRX system-level design methodology as the key driver in enabling performance optimization for achieving a wide frequency range of operation at lowest power and area consumption. By employing an optimized architecture constructed on available state-of-the-art 28 nm functional building blocks, the monolithic SDTRX consists of a mixer-based harmonic rejection RX with a digital-to-analog converter-based TX and a smart phase-locked loop system. It operates over 0.4–1.7 GHz frequency range while consuming less than 475 mW in half-duplex mode. Moreover, by developing a simple transmitter (TX) to receiver (RX) loopback circuit, the system is enabled to efficiently calibrate TX output power and to remove the need for a dedicated external pin. This low-cost SDTRX is embedded in various 28 nm CMOS multimedia system-on-chip and is, to the authors’ knowledge, the first reported transceiver front-end to enable true HSD streaming within home cable networks.