Simon M. Tam

Lucky-electron model of channel hot-electron injection in MOSFET'S

The lucky-electron concept is successfully applied to the modeling of channel hot-electron injection in n-channel MOSFETs, although the result can be interpreted in terms of electron temperature as well. This results in a relatively simple expression that can quantitatively predict channel hot-electron injection current in MOSFETs. The model is compared with measurements on a series of n-channel MOSFETs and good agreement is achieved. In the process, new values for many physical parameters such as hot-electron scattering mean-free-path, impact-ionization energy are determined. Of perhaps even greater practical significance is the quantitative correlation between the gate current and the substrate current that this model suggests.

Hot-electron-induced photon and photocarrier generation in Silicon MOSFET's

The phenomenon of and the physical mechanisms for the generation of minority carriers in the substrate of NMOS and CMOS are studied. Secondary impact ionization is not responsible. The responsible mechanisms are hot-electron-induced photocarrier generation and, under extreme conditions, forward biasing of the source-substrate junction. The photon generation is believed to be due to the bremsstrahlung of the channel hot electrons. A theoretical model based on the lucky electron concept and the bremsstrahlung mechanism is proposed. The calculated characteristics of photon generation agree well with experimental results. About 2 × 10-5photogenerated minority carriers are generated for every (primary) impact-ionization event in NMOSFET. Photocarrier-induced leakage current can be fitted with either an inverse square dependence on distance or an exponential dependence with an effective decay length of about 780 µm.

Clock generation and distribution for the first IA-64 microprocessor

Increased functionality and performance in todays microprocessors has resulted in a trend toward larger die sizes and higher operating frequencies. These factors, coupled with larger on-die variations at reduced device geometries, call for special management of the clock distribution skew. The clock generation and distribution for the first IA-64 microprocessor achieves a low skew by using distributed programmable deskew units. Local skew control compensates for load mismatches and within-die process variations, as well as temperature and voltage gradients. In addition, this design supports debug features including on-die clock shrink and test access port (TAP) control of the deskew settings.

An analytical breakdown model for short-channel MOSFET's

Avalanche-induced breakdown mechanisms for short-channel MOSFETs are discussed. A simple analytical model that combines the effects due to the ohmic drop caused by the substrate current and the positive feedback effect of the substrate lateral bipolar transistor is proposed. It is shown that two conditions must be satisfied before breakdown will occur. One is the emission of minority carriers into the substrate from the source junction, the other is sufficient avalanche multiplication to cause significant positive feedback. Analytical theory has been developed with the use of a published model for short-channel MOSFETs. The calculated breakdown characteristics agree well with experiments for a wide range of processing parameters and geometries.

A 45 nm 8-Core Enterprise Xeon¯ Processor

This paper describes a 2.3 Billion transistors, 8-core, 16-thread, 64-bit Xeon® EX processor with a 24 MB shared L3 cache implemented in a 45 nm nine-metal process. Multiple clock and voltage domains are used to reduce power consumption. Long channel devices and cache sleep mode are used to minimize leakage. Core and cache recovery improve manufacturing yields and enable multiple product flavors from the same silicon die. The disabled blocks are both clock and power gated to minimize their power consumption. Idle power is reduced by shutting off the unterminated I/O links and shedding phases in the voltage regulator to improve the power conversion efficiency.

A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache

This paper describes a dual-core 64-b Xeon MP processor implemented in a 65-nm eight-metal process. The 435-mm2 die has 1.328-B transistors. Each core has two threads and a unified 1-MB L2 cache. The 16-MB shared, 16-way set-associative L3 cache implements both sleep and shut-off leakage reduction modes. Long channel transistors are used to reduce subthreshold leakage in cores and uncore (all portions of the die that are outside the cores) control logic. Multiple voltage and clock domains are employed to reduce power

Clock generation and distribution for the 130-nm Itanium/sup /spl reg// 2 processor with 6-MB on-die L3 cache

The clock generation and distribution system for the 130-nm Itanium 2 processor operates at 1.5 GHz with a skew of 24 ps. The Itanium 2 processor features 6 MB of on-die L3 cache and has a die size of 374 mm/sup 2/. Fuse-based clock de-skew enables post-silicon clock optimization to gain higher frequency. This paper describes the clock generation, global clock distribution, local clocking, and the clock skew optimization feature.

A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache

A dual-core 64b Xeonreg MP processor is implemented in a 65nm 8M process. The 435mm2 die has 1.328B transistors. Each core has two threads and a unified 1MB L2 cache. The 16MB unified, 16-way set-associative L3 cache implements both sleep and shut-off leakage reduction modes

Active Filter-Based Hybrid On-Chip DC–DC Converter for Point-of-Load Voltage Regulation

An active filter-based on-chip DC-DC voltage converter for application to distributed on-chip power supplies in multivoltage systems is described in this paper. No inductor or output capacitor is required in the proposed converter. The area of the voltage converter is therefore significantly less than that of a conventional low-dropout (LDO) regulator. Hence, the proposed circuit is appropriate for point-of-load voltage regulation for noise sensitive portions of an integrated circuit. The performance of the circuit has been verified with Cadence Spectre simulations and fabricated with a commercial 110 nm complimentary metal oxide semiconductor (CMOS) technology. The area of the voltage regulator is 0.015 mm2 and delivers up to 80 mA of output current. The transient response with no output capacitor ranges from 72 to 192 ns. The parameter sensitivity of the active filter is also described. The advantages and disadvantages of the active filter-based, conventional switching, linear, and switched capacitor voltage converters are compared. The proposed circuit is an alternative to classical LDO voltage regulators, providing a means for distributing multiple local power supplies across an integrated circuit while maintaining high current efficiency and fast response time within a small area.

A 1.5-GHz 130-nm Itanium/sup /spl reg// 2 Processor with 6-MB on-die L3 cache

This 130-nm Itanium 2 processor implements the explicitly parallel instruction computing (EPIC) architecture and features an on-die 6-MB 24-way set-associative level-3 cache. The 374-mm/sup 2/ die contains 410 M transistors and is implemented in a dual-V/sub t/ process with six Cu interconnect layers and FSG dielectric. The processor runs at 1.5 GHz at 1.3 V and dissipates a maximum of 130 W. This paper reviews circuit design and package details, power delivery, the reliability, availability, and serviceability (RAS) features, design for test (DFT), and design for manufacturability (DFM) features, as well as an overview of the design and verification methodology. The fuse-based clock deskew circuit achieves 24-ps skew across the entire die, while the scan-based skew control further reduces it to 7 ps. The 128-bit front-side bus has a bandwidth of 6.4 GB/s and supports up to four processors on a single bus.