Mark A. Holler

Learning on an analog VLSI neural network chip

The issues associated with implementing the error backpropagation algorithm on a 64-neuron nonvolatile analog VLSI neural network chip (ETANN) are described. Imperfections in the analog ETANN chip were identified and found to impose constraints on the learning process. A chip-in-the-loop learning technique and an adaptive, reinforced, bake-train-bake scheme are reported. These techniques have shown potential in surmounting the difficulties connected with learning on an analog neural network chip. Experimental results are reported.<<ETX>>

Implementation and performance of an analog nonvolatile neural network

An integrated circuit implementation of a fully parallel analog artificial neural network is presented. We include details of the architecture, some of the important design considerations, a description of the circuits and finally actual performance data. The electrically trainable artificial neural network (ETANN) chip incorporates 64 analog neurons and 10,240 analog synapses and utilizes a 1-µm CMOS NVM process. The network calculates the dot product between a 64-element analog input vector and a 64 × 64 nonvolatile (EEPROM based) analog synaptic weight array. These calculations occur at a rate in excess of 1.3 billion interconnections per second. All elements of the computation are stored and calculated in the analog domain and strictly in parallel. A 2:1 input and neuron multiplex mode permits rates in excess of 2 billion interconnections per second and a single-chip effective network size of 64 inputs by 128 outputs. The ETANN incorporates differential signal techniques throughout for improved noise rejection. Current summing is employed for the sum of products calculations. The chip integrates approximately 400 op amps, including variable gain stages of from 20 to 54 dB. Inevitable component to component variations due to the use of minimum dimension elements are found not to be significant for operation in an adaptive environment.

A radial basis function neural network with on-chip learning

A radial basis function neural network is implemented in a 0.8 /spl mu/m Flash EPROM CMOS technology. The RBF network is used to estimate probability density functions for the purpose of pattern recognition. At 40 MHz this 3.7 M transistor chip performs 20 billion 5 b integer subtract and accumulate operations/s and 160 MFLOPS.

Analog VLSI neural networks for impact signal processing

The architecture and operation of the 80170NX electrically trainable analog neural network, which recognizes objects in real time, are discussed. The 80170NX uses a discrete Fourier transform (DFT) to preprocess an accelerometer output waveform that is subsequently recognized through a multilayer perceptron neural network. It is shown that neural network hardware operating in a linear mode can perform conventional signal processing functions. The similarity of neural network computations to linear signal processing functions makes it exceedingly straightforward to integrate neural networks and conventional signal processing in the system.<<ETX>>

A 100ns 256K CMOS EPROM

This paper will cover a 256K CMOS EPROM with a 400ns access time achieved by use of address transition detection. Redundancy is implemented with metal-covered EPROM cells.

A 200ns 256k HMOSII EPROM

Using a double poly HMOSII wafer stepper technology, a 4.29mm × 4.29mm 32K×8 EPROM with a 36μ m2cell size has been designed with typical chip access time and power dissipation of 200ns and 350mW, respectively, and a 12V programming mode.

A reconfigurable multi-chip analog neural network: recognition and back-propagation training

A multi-chip analog neural network system capable of prototyping networks with as many as 81920 synaptic connections and 1024 neurons is described. The neural network architecture is reconfigurable by routing all neuron activation values through a host computer which can re-map the network connectivity by changing a look-up table in memory. Once a network is successfully prototyped, it is hardwired and embedded in an application to take full advantage of the performance that the electrically trainable analog neural network (ETANN) chips provide. A multi-layer, multi-chip neural network containing 12660 synaptic connections designed for a pattern recognition application is described along with results. Constraints on network topologies associated with the busing architecture chosen and simulation of this multi-chip system are discussed.<<ETX>>

Extraction of fingerprint orientation maps using a radial basis function recognition accelerator

A ridge direction map, commonly called the orientation map, is essential to most fingerprint identification systems. A novel template matching method for extracting the ridge direction maps from raw fingerprint images is discussed. The method models the intensity profile of fingerprint ridges and generates templates. Subsequently, a radial basis function training procedure reduces the number of prototypical templates. The orientation map directions are then assigned by using a probabilistic measure derived from the contributions of the prototypical templates. A substantial acceleration of the procedure is achieved by using the Ni1000 recognition accelerator.<<ETX>>

Neural network recognition of objects based on impact dynamics

A system is presented which can classify unknown objects by the waveform produced upon their impact with a known object. The output of an accelerometer mounted on the known object is read into a unit that computes the waveforms discrete Fourier transform (DFT), which is then fed into a two-layer neural network recognition module. The specific application described observes a collision between two objects, one of which is a wooden platform while the other is made out of a different material. After being shown sample waveforms produced by collisions with three types of objects, the system can then classify new collisions with the objects within 6 ms after the impact. Both the DFT unit and the classification network are implemented with Intels 80170NX Electrically Trainable Analog Neural Network (ETANN).<<ETX>>

Computer vision in 3D interactivity (panel)

With microprocessor clock rates in excess of 350MHz, SIMD integer instructions commonplace, and shared memory multiprocessing available for under