Sina Balkir

An evolutionary approach to automatic synthesis of high-performance analog integrated circuits

This paper presents an analog integrated circuit synthesis system based on an evolutionary approach. The system contains several novel features. One of these is the high-performance optimization algorithm, which is a combination of evolutionary strategies and simulated annealing. Modeling of dc parameters is done via a fast dc simulator developed for this purpose whereas modeling of ac parameters can be done either with user-defined equations or with neural-fuzzy performance models trained from SPICE simulations. Another novel feature of the system is the incorporation of matching properties of devices. This way, the optimized circuit becomes tolerant to process variations. The synthesis system has been tested on several independent examples and synthesized circuits have been verified functionally with SPICE simulations. Finally, a prototype chip composed of the three examples has been manufactured. The measurement results have demonstrated the validity of the synthesis system on silicon.

A Handheld Neutron-Detection Sensor System Utilizing a New Class of Boron Carbide Diode

A handheld neutron-detection sensor application is described in this paper. The sensor system utilizes a new class of boron carbide diode that interacts with incoming neutrons. To interface with the boron carbide diode, an integrated front end is designed in a 1.5-mum standard CMOS technology. With the diode and front-end microchip, a handheld neutron-detection system was realized with an embedded microcontroller for real-time processing. The handheld detector operation was then tested with a plutonium-beryllium neutron source. Test and measurement results confirm the validity of the approach and the functionality of the design

A CMOS Imager With Focal Plane Compression Using Predictive Coding

This paper presents a CMOS image sensor with focal-plane compression. The design has a column-level architecture and it is based on predictive coding techniques for image decorrelation. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit. The prediction residuals are quantized and encoded by a joint quantizer/coder circuit. To save area resources, the joint quantizer/coder circuit exploits common circuitry between a single-slope analog-to-digital converter (ADC) and a Golomb-Rice entropy coder. This combination of ADC and encoder allows the integration of the entropy coder at the column level. A prototype chip was fabricated in a 0.35 mum CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm times 5.96 mm which includes an 80 times 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.

A CMOS Image Sensor for Multi-Level Focal Plane Image Decomposition

An alternative image decomposition method that exploits prediction via nearby pixels has been integrated on the CMOS image sensor focal plane. The proposed focal plane decomposition is compared to the 2-D discrete wavelet transform (DWT) decomposition commonly used in state of the art compression schemes such as SPIHT and JPEG2000. The method achieves comparable compression performance with much lower computational complexity and allows image compression to be implemented directly on the sensor focal plane in a completely pixel parallel structure. A CMOS prototype chip has been fabricated and tested. The test results validate the pixel design and demonstrate that lossy prediction based focal plane image compression can be realized inside the sensor pixel array to achieve a high frame rate with much lower data readout volume. The features of the proposed decomposition scheme also benefit real-time, low rate and low power applications.

Evolution-based design of neural fuzzy networks using self-adapting genetic parameters

In this paper, an evolution-based approach to design of neural fuzzy networks is presented. The proposed strategy optimizes the whole fuzzy system with minimum rule number according to given specifications, while training the network parameters. The approach relies on an optimization tool, which combines evolution strategies and simulated annealing algorithms in finding the global optimum solution. The optimization variables include membership function parameters and rule numbers which are combined with genetic parameters to create diversity in the search space due to self-adaptation. The optimization technique is independent of the topology under consideration and capable of handling any type of membership function. The algorithmic details of the optimization methodology are discussed in detail, and the generality of the approach is illustrated by different examples.

A Synthesis Tool for CMOS RF Low-Noise Amplifiers

A stand-alone design automation tool tailored for radio frequency (RF) complementary metal-oxide-semiconductor (CMOS) low-noise amplifier (LNA) designs is presented. Rather than relying on commercially available circuit simulators such as Spectre or Hspice, the presented synthesis tool is self-contained with its own built-in modules for faster optimization. Foundry-provided silicon-verified RF device models are incorporated into the synthesis procedure for accurate parasitic modeling. The proposed synthesis tool can be used as an independent circuit design environment for LNAs or, alternatively, as an auxiliary tool generating an initial design for a commercial design environment to reduce design time. To validate the proposed approach, an LNA operating at 900 MHz is synthesized and fabricated in a 0.25-mum CMOS technology. Measurement results are presented, which shows the viability of the proposed synthesis tool.

A quantum dot image processor

A two-dimensional (2-D) periodic array of quantum dots, where each dot is coupled with its nearest neighbors and interfaced with an underlying material exhibiting a negative differential resistance, is theoretically investigated as a dynamical system for image processing. A circuit level study of such a system is performed and the circuit parameters for this paper are extracted by experimentally measuring them in an electrochemically self-assembled quasi-periodic quantum dot array. Large 2-D dot arrays with 4-neighborhood rectangular lattice structure are then simulated and it is shown that if image data are introduced as initial conditions to these arrays, the steady-state response of the system realizes an image processing task similar to edge detection-enhancement. In addition, the quantum dot architecture is capable of horizontal-vertical line detection with a simple arrangement of the coupling resistances between the dots. These applications are demonstrated via numerical experiments.

A compact optimization methodology for single-ended LNA

An equation-based method for the optimization and design of single-ended low noise amplifiers (LNA) is presented. The performance metrics of the LNA such as gain, noise figure and input impedance are formulated in terms of the design variables. The parasitics are included early in the design process and optimal LNA designs satisfying the required specifications are found by the optimizer. Optimal LNA designs based on a 0.35 /spl mu/m CMOS technology obtained by the presented approach are further verified by the spectre simulator of the Cadence design environment. The specifications and performance of the designs are found to be in close agreement, validating the compact optimization technique presented in this work.

ANNSyS (an analog neural network synthesis system)

We present an analog neural network synthesis system based on a circuit simulator and a silicon assembler for neural networks. The circuit simulator makes use of the fact that neural networks with multilayer perceptron architecture consist of many decoupled blocks if the blocks are designed in MOS technology. We implement on-chip training on the software by incorporating the Madaline Rule III into our simulator. The assembler generates the layout by reading the standard cells from a library once the architecture of the network is given.

Evolution based synthesis of analog integrated circuits and systems

An evolutionary approach to automatic synthesis of analog integrated circuits and systems is presented in this paper. An essential feature of this system is a high performance optimization algorithm based on the combination of evolutionary strategies and simulated annealing. As required by analog circuit synthesis, modeling of DC parameters is done via a fast DC simulator developed for this purpose whereas modeling of AC parameters is done either with user-defined equations or with neural-fuzzy performance models trained from SPICE simulations. Another feature of the system is the incorporation of matching properties of devices. The synthesis system has been applied to a number of design cases with demonstrated validity on silicon. The synthesis approach is also considered at the system level for potential analog VLSI applications.