Siva P. Gurrum

Thermal issues in next-generation integrated circuits

The drive for higher performance has led to greater integration and higher clock frequency of microprocessor chips. This translates into higher heat dissipation and, therefore, effective cooling of electronic chips is becoming increasingly important for their reliable performance. We systematically explore the limits for heat removal from a model chip in various configurations. First, the heat removal from a bare chip by pure heat conduction and convection is studied to establish the theoretical limit of heat removal from a bare die bound by an infinite medium. This is followed by an analysis of heat removal from a packaged chip by evaluating the thermal resistance due to individual packaging elements. The analysis results allow us to identify the bottlenecks in the thermal performance of current generation packages, and to motivate lowering of thermal resistance through the board-side for efficient heat removal to meet ever increasing reliability and performance requirements.

Size Effect on the Thermal Conductivity of Thin Metallic Films Investigated by Scanning Joule Expansion Microscopy

A technique to extract in-plane thermal conductivity of thin metallic films whose thickness is comparable to electron mean free path is described. Microscale constrictions were fabricated into gold films of thicknesses 43 nm and 131 nm. A sinusoidal voltage excitation across the constriction results in a local temperature rise. An existing technique known as scanning joule expansion microscopy, measures the corresponding periodic thermomechanical expansion with a 10 nm resolution and determines the local temperature gradient near the constriction. A three-dimensional finite-element simulation of the frequency-domain heat transfer fits the in-plane thermal conductivity to the measured data, finding thermal conductivities of 82±7.7 W/mK for the 43 nm film and 162±16.7 W/mKfor the 131 nm film, at a heating frequencies of 100 kHz and 90 kHz, respectively. These values are significantly smaller than the bulk thermal conductivity value of 318 W/mK for gold, showing the electron size effect due to the metal-dielectric interface and grain boundary scattering. The obtained values are close to the thermal conductivity values, which are derived from electrical conductivity measurements after using the Wiedemann-Franz law. Because the technique does not require suspended metal bridges, it captures true metal-dielectric interface scattering characteristics. The technique can be extended to other films that can carry current and result in Joule heating, such as doped single crystal or polycrystalline semiconductors.

THERMAL MANAGEMENT OF HIGH TEMPERATURE PULSED ELECTRONICS USING METALLIC PHASE CHANGE MATERIALS

A feasibility study for using metallic solid-liquid phase change materials (PCMs) in periodic power dissipating devices is reported. Thermal enhancement has been studied with PCM enclosed inside microchannels within semiconductor devices. Benchmarking experiments were performed with PCM inside copper microchannels and compared with numerical predictions. PCMs perform well at lower power levels for silicon carbide semiconductor devices, but the use of high thermal conductivity spreaders such as diamond becomes mandatory at the higher power levels projected in future applications. PCM effectiveness and temperature reductions as a function of chip thickness, channel width, and power dissipated are presented. Temperature reductions up to 25°C can be realized with a combination of diamond spreaders and PCM filled microchannels.

Generic thermal analysis for phone and tablet systems

Thermal management of handheld systems such as smart phones and tablet systems is becoming increasingly challenging due to increasing power dissipation. These mobile systems pose a significant challenge for implementation of traditional cooling schemes such as heat sinks and fans due to form factor limitations. Instead, new advanced cooling schemes have been developed. This article presents thermal model development from an analysis of todays smart phone thermal management schemes and application of these techniques to a tablet system. Application processor temperature rise and tablet skin temperature are reported for thermal enhancement simulations using this tablet system. Some guiding principles are provided for efficient thermal design of handheld systems.

A Compact Approach to On-Chip Interconnect Heat Conduction Modeling Using the Finite Element Method

Over upcoming electronics technology nodes, shrinking feature sizes of on-chip interconnects and correspondingly higher current densities are expected to result in higher temperatures due to self-heating. This study describes a finite element based compact thermal modeling approach to investigate the effects of Joule heating on complex interconnect structures. In this method, interconnect cross section is assumed to be isothermal and conduction along the interconnect is retained. A composite finite element containing both metal and dielectric regions is used to discretize the interconnect stack. The compact approach predicts the maximum temperature rise in the metal to within 5-10% of the detailed numerical computations, while requiring only a fraction of elements. Computational time for the compact model solution is several seconds, versus many hours for the detailed solutions obtained through successive mesh refinement until grid independence is achieved. For a comparable number of elements, the compact model is in general much more accurate than the traditional finite element approach. To validate the simulations, temperature rise in a 500-link two-layer interconnect with a via layer was measured at several current densities. The compact method predicts the temperature rise of the 500-link chain to within 5% of the measurements thereby validating the method. The approach described here could be an efficient technique for full chip Joule heating simulations and for clock signal propagation simulations, which are performed as part of designing next generation chip architectures.

A semianalytical solution for the 3ω method including the effect of heater thermal conduction

A semianalytical solution for the 3ω method is derived to account for thermal conduction within the metallic heater. The existing uniform heat flux approximation between the metal heater and substrate is replaced by a more realistic uniform heat generation condition within the metal heater. Although this correction does not affect thermal conductivity measurements in the original 3ω method, it is shown that significant errors can result when it is applied for thermal conductivity anisotropy measurements. For low thermal conductivity films, the error in the anisotropy ratio can be as high as 50%.

Numerical simulation of electron transport through constriction in a metallic thin film

Electron transport through a constriction in a thin metallic film of finite thickness is simulated by numerically solving the Boltzmann transport equation (BTE) within the relaxation time approximation under linear response conditions. Such a structure closely represents vias connecting metal levels of different widths. Predicted reduction in effective electrical conductance due to electron surface scattering, which is significant when the dimensions are of the order of carrier mean free path, is compared with that for a constriction between semi-infinite spaces available in the literature. A simple expression for the size effect on conductance is fit to the simulated results applicable for constriction in a finite size thin film. The results could enable better estimate of effective resistance of next generation on-chip interconnections.

A multiscale modeling and experimental study of underfill flow and void formation for flip-chip packages

This paper uses a validated, two-dimensional global underfill flow model previously developed by the authors [1] to examine the effects of substrate surface (ceramic vs. organic) and temperature-dependent underfill viscosity on underfill flow-out time, flow front shape, and void formation during the flip chip encapsulation process. Model predictions are validated by experiments using bumped quartz dies that allow for direct visualization of the underfill infiltration process. In addition, a full three-dimensional underfill flow model is developed to quantify the effect of slanted and convex-shaped solder bumps. The filler particle inhomogeneity due to settling and shear migration is also accounted for in the model. The present study seeks to provide a comprehensive understanding of concurrent effects in the flip-chip underfilling process.

Scanning Joule Expansion Microscopy of a Constriction in Thin Metallic Film

Figure 1: Scanning Joule Expansion Microscopy (SJEM ) setup. The interconnect is periodically heated to i nduce a vertical thermal expansion that causes the cantilev er to oscillate at the same frequency. The lock-in amplif ier measures the amplitude of this particular frequency . The heating frequency is made much higher than the feed back bandwidth to the piezoelectric scanner, which thus can detect only the topography. Metal SiO2

Thermal cycling reliability of lead free solder joints on multi-terminal passive components

The ever growing demand for high performance in integrated circuit packaging is driving the requirement for use of multi-terminal passive components like interdigitated capacitors (IDCs), which inherently enable lower equivalent series inductance (ESR) as compared to its multilayer ceramic chip capacitors (MLCC) and low inductance chip capacitor (LICC) counterparts. To complement use of high functionality IDCs for maximum chip to package electrical performance, this study focuses on IDC solder joint reliability, where a combination of factors are investigated for improved package design considerations. In the current study, key surface-mount technology (SMT) parameters that impact passive component solder joint reliability were initially investigated utilizing physical failure analysis (PFA) and limited electrical testing. In addition, impact of solder composition on fatigue life was also evaluated. Though the investigation was useful in establishing qualitative trends, it had two major drawbacks: 1. Component level reliability analysis provides a step function view of the solder joint integrity, thus true characteristic life cannot be estimated as the samples are removed at specific read-points and examined. 2. Statistically significant data collection is not practical due to time/resource intensive failure analysis. To address these two shortcomings, daisy chain test vehicles were designed with ten-terminal (10T) IDCs. Specific daisy chain nets on 10T caps enabled in situ monitoring of solder joints between the IDC pad and substrate during board-level reliability (BLR) temperature cycling test by routing them to non-critical BGA locations. Detailed PFA was used to calibrate the finite element model, which was then utilized to investigate the impact of chip-cap location and orientation on IDC solder joint reliability