Darvin R. Edwards

Kirkendall void formation in eutectic SnPb solder joints on bare Cu and its effect on joint reliability

The electronic packaging industry has been using electroless Ni(P)∕immersion Au as bonding pads for solder joints. Because of the persistence of the black pad defect, which is due to cracks in the pad surface, the industry is looking for a replacement of the Ni(P) plating. Several Cu-based candidates have been suggested, but most of them will lead to the direct contact of solder with Cu in soldering. The fast reaction of solder with Cu, especially during solid state aging, may be a concern for the solder joint reliability if the package will be used in a high temperature environment and is highly stressed. In this work, the reaction of eutectic SnPb solder with electrodeposited laminate Cu is studied. Emphasis is given to the evolution of the microstructure in the interfacial region during solid state aging and its effect on solder joint reliability. A large number of Kirkendall voids were observed at the interface between Cu3Sn and Cu. The void formation resulted in weak bonding between solder and Cu and...

Effect of thermal aging on board level drop reliability for Pb-free BGA packages

The drive for Pb-free solders in the microelectronics industry presents several new reliability challenges. Examples include package compatibility with higher process temperatures, new solder compound failure mechanisms, and the selection of the proper Pb-free alloy to maximize product lifetime. In addition to the challenges posed by the Pb-free material conversion, the migration of market focus from desktop computing to portable applications is changing the critical system failure mode of interest from conventional temperature cycling (T/C) induced solder fatigue opens to drop impact induced solder joint fracture. In this paper a study was conducted to investigate the influence of intermetallic compound (IMC) growth on the solder joint reliability of Pb-free ball grid array (BGA) packages under drop loading conditions. Thermal aging at homologous temperatures between 0.76 and 0.91 with microstructural analysis was conducted to analyze the solid phase IMC growth at the solder to BGA pad interface. Component level,ball shear and pull tests were also conducted to investigate the aging effect on solder joint strength. A key finding from this work is that Kirkendall voids formed at the bulk solder to package bare Cu pad interface under relative low 100/spl deg/C aging. Void formation and coalesce is shown to be the dominant mechanism for solder joint strength and board level drop reliability degradation.

Shear Stress Evaluation of Plastic Packages

A study has been performed to determine the impact of package assembly on shear stress phenomena in plastic encapsulated integrated circuits (ICs). Test structures were used which allowed quantitative measurements of compressive stresses along with qualitative observation of shear Stress effects. Results from experiments with various mold compounds, lead frame materials, and mount compounds Will be presented. The experiments led to the development of a simplified stress model which can be applied to evaluating package and chip designs of future products.

Constitutive Behavior of Sn3.8Ag0.7Cu and Sn1.0Ag0.5Cu Alloys at Creep and Low Strain Rate Regimes

Constitutive models for SnAgCu solder alloys are of great interest at the present. Commonly, constitutive models that have been successfully used in the past for Sn-Pb solders are used to describe the behavior of SnAgCu solder alloys. Two issues in the modeling of lead-free solders demand careful attention: 1) Lead-free solders show significantly different creep strain evolution with time, stress and temperature, and the assumption of evolution to steady state creep nearly instantaneously may not be valid in SnAgCu alloys and 2) Models derived from bulk sample test data may not be reliable when predicting deformation behavior at the solder interconnection level for lead-free solders due to the differences in the inherent microstructures at these different scales. In addition, the building of valid constitutive models from test data derived from tests on solder joints must de-convolute the effects of joint geometry and its influence on stress heterogeneity. Such issues have often received insufficient attention in prior constitutive modeling efforts. In this study all of the above issues are addressed in developing constitutive models of Sn3.8Ag0.7Cu and Sn1.0Ag0.5Cu solder alloys, which represent the extremes of Ag composition that have been mooted at the present time. The results of monotonic testing are reported for strain rates ranging from 4.02E-6 to 2.40E-3 s-1. The creep behavior at stress levels ranging from 7.8 to 52 MPa is also described. Both types of tests were performed at temperatures of 25degC, 75degC and 125degC. The popular Anand model and the classical time-hardening creep model are fit to the data, and the experimentally obtained model parameters are reported. The test data are compared against other reported data in the literature and conclusions are drawn on the plausible sources of error in the data reported in the prior literature.

Multichip assembly with flipped integrated circuits

A multichip module process has been developed using flipped-chip interconnection. The process uses plated copper bumps for superior thermal transport characteristics, active silicon as a substrate material for matched expansion properties, on-chip interconnection metallization that allows bumps to be placed over the active circuitry, and conventional wafer fabrication facilities for low-cost production. For successful design and fabrication of multichip assemblies, an organized methodology similar to that which has proved successful in design and assembly of single VLSI circuits was used. This approach involves: computer-aided modeling of the circuit and package for electrical, thermal, and mechanical simulation; test chips for process development and failure mechanism testing; and fabrication of actual demonstration circuits. Verification of function and reliability was then made through temperature cycle testing (-65 degrees C to 150 degrees C), exposure to accelerated moisture environments, and measure of heat dissipation properties. This approach and an example of its application to a multichip module that demonstrated successful performance on the first design pass are described. >

Wire bonds over active circuits

A reliable process-for wire bonding over active integrated circuits, which are subsequently assembled in plastic packages, has been developed. This technology accommodates reducing the silicon die area required for bond pads and for on-chip bussing. Further, it supports area array wire bonding by allowing larger bond pads with relaxed pitch without sacrificing silicon area. This is accomplished by processing an additional metal layer on the wafers protective overcoat for bond pad and bussing metallization. A stress buffer layer of polyimide is applied between the inorganic overcoat and top metal layer. Material characteristics and process requirements that are fully compatible with existing wafer fabrication technology and the wire bond technology required for assembly are defined. Design rules for implementing the process in new chip designs are given. Accelerated reliability tests performed on double-level metal logic devices show no degradation due to these new processes.<<ETX>>

Test Structure Methodology of IC Package Material Characterization

A methodology in assembly/packaging technology of semiconductor integrated circuits (ICs) is described Which serves a threefold purpose: it aims at characterizing and selecting electronic assembly/Packaging materials; it directs optimization and control of assembly/packaging processes; and it identifies failure mechanisms which determine product reliability. Case example applications of the methodology are reported including application to package molding compound characterization arid chip mount material selection. Conclusions are given in which a broadening of the methodology tO identify early warning indicators for prediction of later reliability failures is discussed.

Experimental evaluations of the strength of silicon die by 3-point-bend versus Ball-on-Ring tests

Silicon wafers and dies are made of single crystalline material in semiconductor applications which must withstand high stresses within electronic packages. The apparent mechanical strength of single-crystalline Si depends on process induced defects. Mechanical bending tests are the simplest way to obtain the strength of Si dies and wafers and have been used for many years throughout the industry. Some of the bending tests, such as the 3-point-bend (3PB) test, provide a convoluted contribution from both the defects on die surface (caused by backgrinding and mishandling) and defects on die edges (caused by sawing or dicing). However, the ball-on-ring (BOR) test provides a way to single out the contribution of backside grinding defects to the die strength. This paper compares the results of both 3PB and BOR tests on a number of backgrinding and dicing processes. The die strength of the 3PB test is consistently less than that of the BOR test due to the fact that the edge defects are under tension for 3PB tests but not for BOR. It is demonstrated that the BOR test is a good method for backgrinding process optimization. Due to the intrinsic scattering nature of the strength data, a Weibull-based probabilistic mechanics approach is the method of choice to present the data.

Development of JEDEC standard thermal measurement test boards

A combination of experimental and modeling studies has been performed to define the impact of printed circuit board (PCB) design on the measured thermal performance of IC packages. These results have been used to develop a JEDEC test card standard that allows less than 10% measurement variability between the minimum and maximum limits of the design parameters. At the same time, the standard allows wide latitude in layout for various components. The modelling and measurement studies that were performed to set the limits of the standard test coupons for surface mounted components and area array packages such as ball grid arrays (BGAs) will be described, along with extensions in principle to actual devices operating in systems.

Generic thermal analysis for phone and tablet systems

Thermal management of handheld systems such as smart phones and tablet systems is becoming increasingly challenging due to increasing power dissipation. These mobile systems pose a significant challenge for implementation of traditional cooling schemes such as heat sinks and fans due to form factor limitations. Instead, new advanced cooling schemes have been developed. This article presents thermal model development from an analysis of todays smart phone thermal management schemes and application of these techniques to a tablet system. Application processor temperature rise and tablet skin temperature are reported for thermal enhancement simulations using this tablet system. Some guiding principles are provided for efficient thermal design of handheld systems.