Siva Yellampalli

Dynamically mapping tasks with priorities and multiple deadlines in a heterogeneous environment

In a distributed heterogeneous computing system, the resources have different capabilities and tasks have different requirements. To maximize the performance of the system, it is essential to assign the resources to tasks (match) and order the execution of tasks on each resource (schedule) to exploit the heterogeneity of the resources and tasks. Dynamic mapping (defined as matching and scheduling) is performed when the arrival of tasks is not known a priori. In the heterogeneous environment considered in this study, tasks arrive randomly, tasks are independent (i.e., no inter-task communication), and tasks have priorities and multiple soft deadlines. The value of a task is calculated based on the priority of the task and the completion time of the task with respect to its deadlines. The goal of a dynamic mapping heuristic in this research is to maximize the value accrued of completed tasks in a given interval of time. This research proposes, evaluates, and compares eight dynamic mapping heuristics. Two static mapping schemes (all arrival information of tasks are known) are designed also for comparison. The performance of the best heuristics is 84% of a calculated upper bound for the scenarios considered.

Dynamic mapping in a heterogeneous environment with tasks having priorities and multiple deadlines

In a distributed heterogeneous computing system, the resources have different capabilities and tasks have different requirements. To maximize the performance of the system, it is essential to assign resources to tasks (match) and order the execution of tasks on each resource (schedule in a manner that exploits the heterogeneity of the resources and tasks. The mapping (defined as matching and scheduling) of tasks onto machines with varied computational capabilities has been shown, in general, to be an NP-complete problem. Therefore, heuristic techniques to find a near-optimal solution to this mapping problem are required. Dynamic mapping is performed when the arrival of tasks is not known a priori. In the heterogeneous environment considered in this study, tasks arrive randomly, tasks are independent (i.e., no communication among tasks), and tasks have priorities and multiple deadlines. This research proposes, evaluates, and compares eight dynamic heuristics. The performance of the best heuristics is 83% of an upper bound.

Numerical Modeling of the I-V Characteristic of Carbon Nanotube Field Effect Transistors (CNT-FETs)

Using derived equations for the potential description for carbon nanotube field effect transistors (CNT-FETs), basic semiconductor equations for carbon nanotubes have been used to model the charge transport. The carbon nanotube has been modeled as a line of charge, and a numerical model has been implemented for the current transport. This numerical model uses MATLAB capabilities to solve the given current and voltage equations numerically and presents I-V characteristics for any given CNT-FET.

Built-in Current Sensor for High Speed Transient Current Testing in Analog CMOS Circuits

In this paper, we present a new built-in current sensor (BICS) for high speed, low voltage degradation transient current (IDDT) testing. This sensor has been designed using forward bias technique to limit the supply voltage degradation caused during transient current peaks to 2% of the supply voltage. A CMOS operational amplifier designed for operation at plusmn2.5 V in 0.5 mum n-well CMOS process is used as the circuit under test (CUT). The faults simulating possible short and bridging defects are introduced using the fault injection transistors (FIT). A total of twenty short faults have been introduced into the CUT and nineteen of them were detected, giving 95% fault coverage.

Delta-IDDQ Testing of a CMOS 12-Bit Charge Scaling DigitaltoAnalog Converter

We present design, implementation and test of a built-in current sensor for Delta-IDDQ testing of a CMOS 12-bit charge scaling digital-to-analog converter (DAC). The sensor uses power discharge method for the fault detection. The integrated sensor and the DAC on a chip have been designed and implemented in a 0.5 mum n-well CMOS technology. The DAC uses charge scaling method for the design and a low voltage (0 to 2.5 V) folded cascode op-amp. The built-in current sensor (BICS) has a resolution of 0.5 muA. Faults have been introduced into the DAC using fault injection transistors (FITs). Fault detection by the BICS has been verified both from simulation and experimental measurements.

A combined oscillation, power supply current and I/sub DDQ/ testing methodology for fault detection in floating gate input CMOS operational amplifier

A technique integrating the oscillation, power supply current and I/sub DDQ/ based testing of circuit under test (CUT) is presented. A CMOS operational amplifier with floating gate input transistors, designed for operation at /spl plusmn/2.5 V in 1.5 /spl mu/m n-well CMOS process, is used as the CUT. The faults simulating possible short and open manufacturing defects are introduced using the fault injection transistors. The change in oscillation frequency, power supply current and quiescent current is observed for fault detection. Two op-amps have been designed, one with twenty two short faults and the other with a combination of five open and seven short faults. Twenty two short faults and twelve combined open and short faults (except two short faults) have been detected by the combined testing methodology.

A combined noise analysis and power supply current based testing of CMOS analog integrated circuits

A technique integrating the noise analysis based testing and the conventional power supply current testing of CMOS analog integrated circuits is presented for bridging type faults due to manufacturing defects. The circuit under test (CUT) is a CMOS amplifier designed for operation at ± 2.5 V and implemented in 1.5 μm CMOS process. The faults simulating possible manufacturing defects have been introduced using the fault injection transistors. The amplifier circuit is analyzed and simulated in SPICE for its performance with and without fault injections. The faults in the CUT are identified by observing the variation in the equivalent noise voltage at the output of CUT. In power supply current testing, the current (IPS) through the power supply voltage, VDD is measured under the application of an AC input stimulus. The effect of parametric variation is taken into consideration by determining the tolerance limit using the Monte-Carlo analysis. The fault is identified if the power supply current, IPS lies outside the deviation given by Monte-Carlo analysis. Simulation results are in close agreement with the corresponding experimental values.

Combined oscillation and I DDQ testing of a CMOS amplifier circuit

A simple test methodology is presented, combining oscillation and quiescent power supply current (I DDQ) testing for detecting bridging and open faults in a CMOS amplifier circuit formed during fabrication. The testing is performed at room temperature (300 K) and also at liquid-nitrogen temperature (77 K) to enhance fault detection. An on-chip built-in current sensor has been integrated to monitor I DDQ of the circuit under test. A simple fault-injection technique has been used for simulating manufacturing defects. The amplifier was designed for operation at ±2.5 V in a standard 1.5 μm n-well CMOS process. It is shown that all faults can be detected through a combined oscillation and I DDQ testing method. Theoretical results obtained from SPICE simulations are in close agreement with the corresponding experimental results on fabricated devices.

Built-in Current Sensor for Quiescent Current Testing in Analog CMOS Circuits

In this paper we present a new built in current sensor (BICS) for quiescent current testing- IDDQ. This sensor has been designed using forward bias technique to limit the supply voltage degradation caused by quiescent current passing through the BICS to 2% of the supply voltage. A CMOS operational amplifier designed for operation at plusmn 2.5 V in 0.5 mum n-well CMOS process is used as the circuit under test (CUT). The faults simulating possible short and bridging defects are introduced using the fault injection transistors (FIT). A total of twenty short faults have been introduced into the CUT and nineteen of them been detected giving 95% fault coverage.

A comparator-based I/sub DDQ/ testing of CMOS analog and mixed-signal integrated circuits

A new built-in current sensor (BICS) has been proposed in this paper for the detection of open and short faults. The BICS compares the quiescent current from the circuit under test (CUT) with the reference current. If a fault is detected it gives /spl plusmn/2.5 V at the output depending on the nature of defect. A two stage CMOS op-amp, 3 bit flash architecture based ADC, 3 bit charge scaling architecture based DAC have been used as the CUT. The faults in the circuits have been introduced using fault injection transistors (FITs). A combination of nine open and short faults has been randomly embedded in the op-amp. Twenty three faults were embedded in 3 bit ADC and ten faults were embedded in 3 bit DAC.