Ashok Srivastava

Carbon nanotubes for next generation very large scale integration interconnects

We investigated the application of one-dimensional fluid model in modeling of electron transport in carbon nanotubes and equivalent circuits for interconnections and compared the performances with the currently used copper interconnects in very-large-scale integration (VLSI) circuits. In this model, electron transport in carbon nanotubes is regarded as quasi one-dimensional fluid with strong electron-electron interaction. Verilog-AMS in Cadence/Spectre was used in simulation studies. Carbon nanotubes of the types single-walled, multiwalled and bundles were considered for ballistic transport region, local and global interconnections. Study of the S-parameters showed higher transmission efficiency and lower reflection losses. Theoretical modeling and computer-aided simulation studies through a complimentary CNT-FET inverter pair, interconnected through a wire, exhibited reduced delays and power dissipations for carbon nanotube interconnects in comparison to copper interconnects in 22 nm and lower technology nodes. The performance of CNT interconnects was shown to be further improved with increase in number of metallic carbon nanotubes. Our study suggests the replacement of copper interconnect with the multiwalled and bundles of single-walled carbon nanotubes for the sub-nanometer CMOS technologies.

Integrated adaptive DC/DC conversion with adaptive pulse-train technique for low-ripple fast-response regulation

Dynamic voltage scaling (DVS) is a very effective low-power design technique in modem digital IC systems. On-chip adaptive DC/DC converter, which provides adjustable output voltage, is a key component in implementing DVS-enabled system. This paper presents a new adaptive DC/DC converter design, which adopts a delay-line controller for voltage regulation. With a proposed adaptive pulse-train technique, ripple voltages are reduced by 50%, while the converter still maintains satisfying transient response. With a supply voltage of 3.3V, the output of the converter is well regulated from 1.7 to 3.0V. Power consumption of the controller is below 100 /spl mu/W. Maximum efficiency of 92% is achieved with output power of 125mW. Chip area is 0.8 /spl times/ 1.2mm/sup 2/ in 1.5 /spl mu/m standard CMOS process.

A simple built-in current sensor for I DDQ testing of CMOS data converters

This paper presents a simple built-in current sensor (BICS) design for quiescent current (IDDQ) testing of CMOS data converter circuits. The proposed BICS works in two modes: the normal mode and the test mode. In the normal mode, the BICS is isolated from the circuit under test (CUT) due to which there is no performance degradation of the circuit. In the testing mode, the BICS detects the abnormal current caused by permanent manufacturing defects and has negligible impact on the performance of the circuit under test. The dynamic current of the CUT does not affect the BICS output. The BICS is operated from power supply voltages of the CUT using the current reference configuration. A 10-bit charge scaling digital-to-analog converter and a first-order modulator of an 8-bit sigma delta analog-to-digital converter have been designed in standard 1.5 µm CMOS and tested using the present BICS for injected faults simulating manufacturing defects. It is shown that significant improvement in testing of mixed signal integrated circuits has been achieved using a simple fault injection technique combined with the BICS.

Carrier Density and Effective Mass Calculations for Carbon Nanotubes

The electronic structure of carbon nanotubes has been examined and recalculated using previous theoretical and experimental results. The effective mass and intrinsic carrier concentration have been calculated for different carbon nanotubes. These results show how different diameters and wrapping angles of carbon nanotubes can change their electronic properties. Since the intrinsic carrier concentration of a carbon nanotube can be adjusted, it allows die designer to use the same material (carbon nanotube) for a wide range of applications only by varying the chiral vector (n,m). The calculations performed in this work set an upper limit for a wide range of applications, including carbon nanotube interconnects and carbon nanotube field effect transistors.

A Thermal Model for Carbon Nanotube Interconnects

In this work, we have studied Joule heating in carbon nanotube based very large scale integration (VLSI) interconnects and incorporated Joule heating influenced scattering in our previously developed current transport model. The theoretical model explains breakdown in carbon nanotube resistance which limits the current density. We have also studied scattering parameters of carbon nanotube (CNT) interconnects and compared with the earlier work. For 1 µm length single-wall carbon nanotube, 3 dB frequency in S12 parameter reduces to ~120 GHz from 1 THz considering Joule heating. It has been found that bias voltage has little effect on scattering parameters, while length has very strong effect on scattering parameters.

An Adaptive Body-Bias Generator for Low Voltage CMOS VLSI Circuits

A CMOS body-bias generating circuit has been designed for generating adaptive body-biases for MOSFETs in CMOS circuits for low voltage operation. The circuit compares the frequency of an internal ring oscillator with an external reference clock. When the reference clock is “high,” forward body-bias is generated. When the reference clock is “low,” a reverse body-bias is generated. The forward body bias is limited to no more than 0.4 V to avoid CMOS latchup. The reverse body bias is limited to 0.4 V and is very effective in suppressing the subthreshold current. The frequency adaptive body-bias generator circuit has been implemented in standard 1.5 μm n-well CMOS technology and simulated using SPICE. Excellent agreement is obtained between the simulated output characteristics and the corresponding experimentally measured behavior. It is also demonstrated that up to 90% leakage current in CMOS circuits can be reduced by applying the adaptive bias generator to lower threshold voltage CMOS circuits. The design is simple and can be embedded in low power CMOS designs such as the physical nodes of wireless sensor networks.

Analytical Current Transport Modeling of Graphene Nanoribbon Tunnel Field-Effect Transistors for Digital Circuit Design

A semi-classical and a semi-quantum current transport model for p-i-n n-type armchair graphene nanoribbon tunnel field effect transistor (TFET) are studied analytically. The results are compared with the numerical quantum transport simulation method using an atomistic Schrodinger-Poisson solver within the non-equilibrium Green function (NEGF) formalism. The channel length and width are 20 and 4.9 nm and a-GNR band gap is 0.289 eV. Current ratio ION/IOFF at 0.1 V supply voltage is calculated as follows: 122, 16.3 and 116 with a subthreshold slopes 26, 69 and 27.4 mV/decade from semi-classical, semi-quantum and NEGF simulation, respectively. Performance of a-GNR TFET is also studied analytically and numerically considering a-GNR width variation. Voltage transfer characteristics of a-GNR TFET inverter are computed for 0.1 V and 0.2 supply voltages using three current transport models which are in close agreement.

Emerging carbon nanotube electronic circuits, modeling and performance

In this paper, a CNT interconnect model is presented and combined with a CNT-FET model to study the performance of CNT-FET circuits at very high frequencies. An all complementary CNT-FET inverter pair using CNT interconnection is modeled and characterized. Cadence/Spectre simulations show that CNT-FET circuits can operate at GHz frequencies and CNT interconnects are able to provide enough bandwidth for GHz operation of CNT-FETs circuits.

A novel approach to I/sub DDQ/ testing of mixed-signal integrated circuits

This paper presents an effective built-in current sensor (BICS), which has a very small impact on the performance of the circuit under test (CUT). The proposed BICS works in two-modes the normal mode and the test mode. In the normal mode, the BICS is isolated from the CUT due to which there is no performance degradation of the CUT. In the testing mode, our BICS detects the abnormal current caused by permanent manufacturing defects. Furthermore, our BICS can also distinguish the type of defect induced (gate-source short, source-drain short and drain-gate short). Our BICS requires neither an external voltage source nor current source. Hence the BICS requires less area and is more efficient than the conventional current sensors. The circuit under test is a 10-bit digital-to-analog converter using charge-scaling architecture.

Scaling Effects on Static Metrics and Switching Attributes of Graphene Nanoribbon FET for Emerging Technology

In this paper, we have investigated the static metrics and switching attributes of graphene nanoribbon field-effect transistors (GNR FETs) for scaling the channel length from 15 nm down to 2.5 nm and GNR width by approaching the ultimate vertical scaling of oxide thickness. We have simulated the double-gate GNR FET by solving a numerical quantum transport model based on selfconsistent solution of the 3D Poisson equation and 1D Schrödinger equation within the non-equilibrium Greens function formulism. The narrow armchair GNR, e.g. (7,0), improved the device robustness to shortchannel effects, leading to better OFF-state performance considering OFF-current, ION/IOFF ratio, subthreshold swing, and drain-induced barrier-lowering. The wider armchair GNRs allow the scaling of channel length and supply voltage, resulting in better ON-state performance, such as the larger intrinsic cut-off frequency for the channel length below 7.5 nm at smaller gate voltage as well as smaller intrinsic gate-delay time with the constant slope for scaling the channel length and supply voltage. The wider armchair GNRs, e.g. (13,0), have smaller power-delay product for scaling the channel length and supply voltage, reaching to ~0.18 (fJ/μm).