Skye Wolfer

A multigigabit backplane transceiver core in 0.13-/spl mu/m CMOS with a power-efficient equalization architecture

A binary backplane transceiver core in 0.13-/spl mu/m dual-gate low-voltage (LV) CMOS, operating at 0.6-9.6 Gb/s with an area of 0.56 mm/sup 2/, is presented. The core uses two taps of transmit preemphasis and an adaptive receive equalization strategy incorporating one tap of unrolled decision feedback equalization (DFE), a linear equalizer, and a bandwidth control mechanism integrated with the receiver calibration circuitry. The output driver uses a cascode structure to achieve a 1.7-V peak-to-peak (p-p) differential output swing with low area and minimal overhead power. The core has extensive optional test features including a built-in bit error rate (BER) tester, voltage margining circuit, and an on-chip receiver sampling scope. The power varies from 152 to 275 mW as the speed varies from 6.25 to 9.6 Gb/s while maintaining a voltage margin of 30 mV at a BER of 10/sup -15/.

A 0.6 to 9.6Gb/s binary backplane transceiver core in 0.13/spl mu/m CMOS

A backplane transceiver core in 0.13 /spl mu/m dual-gate CMOS, operating at 0.6 to 9.6 Gb/s with an area of 0.56 mm/sup 2/ and dissipating 150 mW at 6.25 Gb/s, is presented. This core uses a unique adaptive receive equalization strategy, transmit pre-emphasis, and has extensive optional test features including a built-in BER tester and an on-chip receiver sampling scope.

The Use of the Manufacturing Sensitivity Model Forms to Comprehend Layout Manufacturing Robustness For Use During Device Design

As semiconductor device manufacturing processes are reducing feature sizes ever smaller, the manufacturing processes are becoming ever more complex. This complexity is having significant impacts on data communications between device design teams and manufacturing process teams. With current manufacturing process constraints, the constraints placed on a design team are difficult to conceptualize, communicate and enforce. This study describes a new type of process model, referred to as a focus sensitivity model that is capable of speeding up the model based analysis of design patterns for manufacturing robustness. The FSM is a difference model based on the photolithography process model. The FSM produces information about multiple process states in one pass. It also produces interpreted data, which removes the need to understand the performance of individual process states. Finally, FSM is capable of analyzing drawn patterns without optical proximity correction applied to determine pattern manufacturability