Sofoklis Plevridis

A single-chip digitally calibrated 5.15-5.825-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a wireless LAN

The drive for cost reduction has led to the use of CMOS technology in the implementation of highly integrated radios. This paper presents a single-chip 5-GHz fully integrated direct conversion transceiver for IEEE 802.11a WLAN systems, manufactured in 0.18-/spl mu/m CMOS. The IC features an innovative system architecture which takes advantage of the computing resources of the digital companion chip in order to eliminate I/Q mismatch and achieve accurately matched baseband filters. The integrated voltage-controlled oscillator and synthesizer achieve an integrated phase noise of less than 0.8/spl deg/ rms. The receiver has an overall noise figure of 5.2 dB and achieves sensitivity of -75 dBm at 54-Mb/s operation, both referred to the IC input. The transmit error vector magnitude is -33 dB at -5-dBm output power from the integrated power-amplifier driver amplifier. The transceiver occupies an area of 18.5 mm/sup 2/.

A digitally calibrated 5.15-5.825GHz transceiver for 802.11a wireless LANs in 0.18/spl mu/m CMOS

This transceiver achieves a transmit 1dB output compression point of +15dBm, and the overall receiver noise figure is 5dB. A power gain range of >45dB/65dB for transmit/receive and a PLL synthesizer frequency range of 4.9 to 5.85GHz with -79dBc/Hz phase noise at 10kHz offset have been measured. The IC is realized in 0.5/spl mu/m SiGe BICMOS technology and occupies 17mm/sup 2/.

A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a/b/g wireless LAN

A single-chip dual-band 5.15-5.35-GHz and 2.4-2.5-GHz zero-IF transceiver for IEEE 802.11a/b/g WLAN systems is fabricated on a 0.18-/spl mu/m CMOS technology. It utilizes an innovative architecture including feedback paths that enable digital calibration to help eliminate analog circuit imperfections such as transmit and receive I/Q mismatch. The dual-band receive paths feature a 4.8-dB (3.5-dB) noise figure at 5.25 GHz (2.45 GHz). The corresponding sensitivity at 54 Mb/s operation is -76 dBm for 802.11a and -77 dBm for 802.11g, both referred at the input of the chip. The transmit chain achieves output 1-dB compression at 6 dBm (9 dBm) at 5 GHz (2.4 GHz) operation. Digital calibration helps achieve an error vector magnitude (EVM) of -33 dB (-31 dB) at 5 GHz (2.4 GHz) while transmitting -4 dBm at 54Mb/s. The die size is 19.3 mm/sup 2/ and the power consumption is 260 mW for the receiver and 320 mW (270 mW) for the transmitter at 5 GHz (2.4 GHz) operation.

A dual-band 4.9-5.95 GHz, 2.3-2.5 GHz, 0.18 /spl mu/m CMOS transceiver for 802.11 a/b/g-802.16d/e

A zero-IF, 4.9-5.95 GHz, 2.3-2.5 GHz, transceiver is fabricated on a 0.18 /spl mu/m CMOS process. By using a fractional-N synthesizer, an integrated phase error of 0.6/spl deg/ (0.7/spl deg/) at 5 GHz (2.4 GHz) is achieved, while supporting fine frequency resolution. Digital calibration eliminates I/Q mismatch and achieves accurately matched baseband filters. The transceiver is compliant to 802.11a/b/g, while programmable bandwidth filters and an EVM of -35 dB in both transmit and receive, make it suitable for applications based on 802.16d/e.

A cost-efficient 0.18 /spl mu/m CMOS RF transceiver using a fractional-N synthesizer for 802.11b/g wireless LAN applications

A single-chip 2.4 GHz, zero-IF transceiver for IEEE 802.11 b/g WLAN systems is fabricated on a 0.18 /spl mu/m CMOS technology. Based on an innovative system architecture using digital calibration, analog circuit imperfections are eliminated. The transceiver features enhanced phase noise performance with the use of a fractional-N synthesizer. A switched configuration allows for the same filters to be used on both TX/RX paths, thus minimizing area. It features a NF of 3.5 dB while the sensitivity is -78 dBm at 54 Mb/s operation, referred at the input of the chip. The transmit output 1 dB compression point is 9 dBm. Digital calibration helps achieve an EVM of -31 dB while transmitting -4 dBm at 54 Mb/s.

A 65nm 3G femtocell multiband transceiver

Last mile residential connectivity and the demand for increased indoor coverage and capacity in 3G cellular systems has led to the commercial introduction of femtocell (Home Node B) base stations. To achieve higher component integration, support additional functionality, and decrease power, there is a need to minimize component count, PCB area and power consumption without sacrificing performance, while also preserving backwards-compatibility with legacy 2G systems. In this paper, we present a 65nm CMOS 3G/HSPA+ femtocell transceiver with 350mW power consumption that eliminates the need for Tx SAW filters. The proposed solution supports 10 TX (Downlink) and 10+10 (Downlink+Uplink) RX UMTS bands from Band I to Band VI and Band VIII to Band XI, quad-band GSM sniffing and GPS band receive capability for soft GPS operation.

9.1 A 13mm 2 40nm multiband GSM/EDGE/HSPA+/TDSCDMA/LTE transceiver

To support increased device functionality and higher data-rates in LTE-enabled systems, while improving user experience and usage time, there is a need to reduce RFIC size and power consumption without degrading performance, while maintaining backward compatibility with legacy 2G/3G systems [1]. This paper introduces a 13mm2, 40nm CMOS 2G/HSPA+/TDSCDMA/UE cat. 4 transceiver that consumes 36/65mA battery-referenced current in 3G/LTE20 modes (B1, -50dBm TX, -60dBm RX). This is achieved in part by employing a multiport single-core LNA with a multitap inductor and a current-mode-driven single-core transmit mixer. Baseband-assisted calibration techniques help achieve <;1.2% RX EVM in LTE20 and >60dBm IIP2 in all bands. To save on platform area and cost, the RFIC supports single-ended LNAs, 32kHz clock generation, and free-running XTAL operation. TX SAW filters are not required.