Rizalafande Che Ismail

An efficient Modified Booth multiplier architecture

We present the design of an efficient multiplication unit. This multiplier architecture is based on radix 4 booth multiplier. In order to improve his architecture, we have made 2 enhancements. The first is to modify the Wen-Changs modified booth encoder (MBE) since it is the fastest scheme to generate a partial product. However, when implementing this MBE with the simplified sign extension (SSE) method, the multiplications output is incorrect. The 2nd part is to improve the delay in the 4:2 compressor circuit. The redesigned 4:2 compressor reduced the delay of the carry signal. This modification has been made by rearranging the Boolean equation of the carry signal. This architecture has been designed using Quartus II. The Gajski rule has been adopted in order to estimate the delay and size of the circuit. The total transistor count for this new multiplier is being a slightly bigger. This is due to the new MBE which is uses more transistor. However in performance speed, this efficiency multiplier is quite good. The propagation delay is reduced by about 2% - 7% from other designers.

High Performance Complex Number Multiplier Using Booth-Wallace Algorithm

This paper presents the methods required to implement a high speed and high performance parallel complex number multiplier. The designs are structured using radix-4 modified Booth algorithm and Wallace tree. These two techniques are employed to speed up the multiplication process as their capability to reduce partial products generation to eta/2 and compress partial product term by a ratio of 3:2. Despite that, carry save-adders (CSA) is used to enhance the speed of addition process for the system. The system has been designed efficiently using VHDL codes for 16 times16-bit signed numbers and successfully simulated and synthesized using ModelSim XE II 5.8c and Xilinx ISE 6.1i. As a proof of concept, the system is implemented on Xilinx Virtex-II Pro FPGA board.

A review of LNA topologies for wireless applications

This paper presents the reviews of few previous works for low noise amplifier design (LNA). This paper will explore several recent architectures of LNA but focused on four techniques of topologies which are forward body bias, self-biased inverter, common source cascade and cascode technique. Those architectures are able to minimize power consumed in a typical CMOS for wireless sensor network (WSN). Besides, high gain, low noise, input and output matching are also reviewed. As to provide extremely low power and also optimized all characteristics aspects, the performance for each topologies then are discussed. Further research will be conducted based on these four topologies comparisons in order to design a new successful LNA.

Arithmetic addition and subtraction function of logarithmic number system in positive region: An investigation

Logarithmic number system or LNS has become an optimal choice in digital image processing instead of floating point (FP) system based on latest researches in LNS. Digital image processing which deals with a lot of complex operations such as multiplication and division, makes LNS as a great choice of implementation. However, the implementation had been restricted by the addition and subtraction function in LNS arithmetic as these functions entail complex procedures and circuitry. As its huge potential to be a substitution of FP, there is an urgent need for LNS to improve the performance of both operations. Hence, various studies had been conducted in this area, however most of the research concern the implementation of these operations in the negative region. Therefore, this study is conducted with the objective on the exploration of both LNS addition and subtraction operations in the positive region and highlights the potential areas for design modifications and improvements. Then, these enhancements will be combined with other arithmetic functions in creating an optimum LNS design to be utilized in any digital image processing system.

The design revolution of logarithmic number system architecture

Logarithmic number system (LNS) has been a trend in digital signal processing (DSP) for recent years, particularly digital image processing. LNS was been implemented in DSP processors and even as an enhancer tool in image improvements. The selection of LNS is due to the ease of operation for multiplication, division, square and square-root which been replaced by fixed-point addition, subtraction, and left- and right-shift operations, respectively. Current researches have found that LNS is possible to be a competitor and a potential replacement of floating point (FP) system in near future, as it provides comparable strength towards the latter. The other arithmetic operations, which is the addition and subtraction, however, have to face great challenges in implementations as it requires complex procedures and circuitry. As LNS potential to be a substitution of FP, there is a significant need for LNS to improve the performance. Hence, this paper outlines the evolution of the LNS architecture design and highlights the potential areas for further improvements. These enhancements will then be implemented and verified in a specific digital image processing system.

High efficiency CMOS Class E power amplifier using 0.13 µm technology

This paper presents the design of a 2.4-GHz CMOS Class E power amplifier (PA) for wireless applications in Silterra 0.13-μm CMOS technology. The Class E PA proposed in this paper is a single-stage PA in a cascode topology in order to minimize the device stress problem. All transistors are arranged in parallel to decrease on-resistance for high efficiency with on-chip input and output impedance matching. The simulation results indicate that the PA delivers 11.9 dBm output power and 53% power added efficiency (PAE) with 1.3-V power supply into a 50-Ω load. The chip layout is 0.27 mm2.

An efficient processing element architecture for pairwise sequence alignment

One of the most challenging tasks in sequence alignment is its repetitive and time-consuming alignment matrix computations. Alignment matrix scores are crucial for identifying regions of homology between biological sequences. In this paper, a parametrizable and area efficient processing element (PE) architecture for performing biological sequence alignment task especially for pairwise biological sequence alignment is designed. Its corresponding PE architecture realization was prototyped on Xilinx FPGA platform. FPGA has been chosen as it able to realize an array of systolic array-based PEs. Execution of the proposed parameterizable PE architecture have been conducted and comparison results have shown that the systolic arrays with parameterizable PE has gained at least 15x speed-up as compared to the well-known SSEARCH 35 solution.

High Power LED Thermal and Stress Simulation on Copper Slug

High power LED are captivating attention due to its cogent impacts on lighting industry in terms of efficacy, low power consumption, long lifetime and miniature physical size. Nonetheless, the efficiency and reliability of the LED is signified by the junction temperature. This work demonstrates the thermal and stress simulation of single chip LED package with 1mm x1mm x 1mm copper heat slug. The simulation was performed using Ansys version 11. The GaN LED chip was powered with input power of 0.1 W and 1 W. The simulation outcome exhibited that at the maximum junction temperature and stress of the LED chip were 115.81°C and 221.56MPa correspondingly for input power of 1W.

Stress and Temperature Simulation Using Copper-Diamond Composite Slug

A revolution to illumination industry, the high power light emitting diodes, LEDs have significant dominance in terms of optical performance, low power consumption and superior reliability over conventional lights. In spite of that the junction temperature of the LED is an imperative aspect which manipulates the consistency of the LED. This study discusses the thermal and stress analysis of single chip LED package with copper diamond heat slug. The simulation was carried out using Ansys version 11. In this simulation, input power of 0.1W and 1W were applied to the LED chip. The key findings of this study exhibited that the max junction temperature of 113.13 °C and stress of 116.36 MPa were gained.

Investigation and design of the efficient hardware-based RNG for cryptographic applications

The best security factor in any encryption algorithm is the random values used in key management or the structure of the algorithm itself. Thus, some of the encryption algorithm employed random number generator to produce this type of numbers. This paper describes the process of selecting the most efficient algorithm to represent the hardware RNG for the usage in cryptography. For this purpose, a number of RNG algorithms are selected and analyzed in terms of the sequences randomness using theoretical simulator analysis. Among of the algorithms, the Inverse Congruential Generator algorithm was chosen based on the analysis as it provides the most high quality random sequence and insensitivity in initial condition. The algorithm was further proceed to the NIST test for non-randomness test and it shown reasonable complexity. The design was proven to be implemented successfully on hardware as it then been designed using Verilog HDL and been simulated and verified using Altera QuartusII 9.0sp2 web edition software. The design utilized 7,711 logic elements of Cyclone EP1C20F400C6. Benefited the usage of FPGA, the design could possibly provide reduction in size of the RNG, low power consumption and low cost production for hardware-based encryption.