Sohya Kudoh

Variability Improvement by Si Surface Flattening of Electrical Characteristics in MOSFETs With High-k HfON Gate Insulator

Variability improvement of metal-oxide-semiconductor field-effect transistors (MOSFETs) characteristics with high-k HfON gate insulator by Si surface flattening was investigated. The Si surface flattening process was carried out by Ar/4.9%H2 anneal utilizing rapid thermal annealing system. The HfON gate insulator was formed by the in-situ Ar/O2 plasma oxidation of HfN utilizing electron cyclotron resonance plasma sputtering followed by the post deposition anneal at 600 °C for 1 min. The Si surface flattening was found to significantly improve the threshold voltage variability (ΔVTH) of MOSFET with HfON gate insulator for the first time. Furthermore, the stability of the device characteristics was improved up to the measurement temperature of 100 °C by introducing the Si surface flattening process.

Formation Mechanism of Atomically Flat Si(100) Surface by Annealing in Ar/H 2 Ambient

In this study, the formation mechanism of an atomically flat Si(100) surface by annealing in Ar/4%H2 ambient utilizing the quartz furnace and its effect on Hf-based Metal/Oxide/Nitride/Oxide/Si diodes were investigated. After the etching of the unintentional oxide layer formed by annealing at 1050–1100°C in Ar/4%H2 ambient, the atomically flat p-Si(100) surface was obtained. Furthermore, it was found that the surface root mean square roughness was decreased with increasing the annealing duration. Finally, it was revealed that the J–V characteristics both of before and after 103 program/erase cycles of Al/HfN0.5/HfO2/HfN1.0/HfO2/p-Si(100) diodes were decreased one order of magnitude by a surface flattening process.

Influence of Si(100) surface flattening process on nonvolatile memory characteristics of Hf-based MONOS structures

Metal-oxide-nitride-oxide-silicon (MONOS) type memory is a promising candidate to replace the conventional floating-gate (FG) type non-volatile memory [1]. Even for MONOS memory with high-k gate stacks, such as the in-situ formation of Hf-based MONOS structure, the scaling is necessary to reduce the operating voltage [2]. However, as the gate stacks scaling, the interface roughness at the gate insulator/Si is one of the critical issues to obtain the high reliability and performance of MIS devices [3]. In our previous report, atomically flat Si(100) surface was formed by annealing in Ar/H2 ambient for the first time [4]. In this study, electrical characteristics of Hf-based MONOS structure on atomically flat Si(100) surface were investigated.