Shun-ichiro Ohmi

NiSi salicide technology for scaled CMOS

Salicide is one of the indispensable techniques for high-performance logic devices and its importance increases as the device dimensions become small towards sub-100 nm and hence, the source/drain sheet resistance becomes large. TiSi2 used popularly as the silicide material has been eventually replaced by CoSi2, because of its relatively stable nature during the salicide process. For sub-100-nm technology node, CoSi2 is expected to be further replaced by NiSi. NiSi has several advantages over TiSi2 and CoSi2 for the ultra-small CMOS process. They are (1) low temperature silicidation process, (2) low silicon consumption, (3) no bridging failure property, (4) smaller mechanical stress, (5) no adverse narrow line effect on sheet resistance, (6) smaller contact resistance for both n- and p-Si, and (7) higher activation rate of B for SiGe poly gate electrode. In this paper, NiSi salicide technology is explained.

Characterization of La2 O 3 and Yb2 O 3 Thin Films for High-k Gate Insulator Application

Rare earth oxides, such as La 2 O 3 and Yb 2 O 3 , deposited on Si(100) were investigated for high-k gate insulator applications. La 2 O 3 has the largest bandgap and smallest lattice energy among the rare earth oxides, whileYb 2 O 3 has a smaller bandgap and larger lattice energy compared to La 2 O 3 . La 2 O 3 showed excellent electrical properties, such as small capacitance equivalent thickness and low leakage current density with smooth film surface and interface after rapid thermal annealing (RTA) at 400-600°C. On the other hand, the surface of Yb 2 O 3 thin film was easily roughened after RTA even at 400°C, and the leakage current density was higher compared to La 2 O 3 . The difference in characteristics for the films was considered to be attributed to the difference of their properties, such as bandgap and lattice energy. La 2 O 3 was able to keep the amorphous phase at least up to 600°C RTA, and this seems promising for future high-k gate insulator applications.

Silicon integrated circuit technology from past to future

Abstract Tremendous progress of the silicon integrated circuits (ICs) has been driven by the downsizing of their components such as MOS field effect transistors (MOSFETs) over 30 years. In order to maintain the progress for future, every dimension of the MOSFETs has to be shrunk continuously with almost the same ratio. However, the dimensions are now close to their limit of downscaling, and further reduction becomes very difficult. In order to solve the problem, the introduction of new materials and structures are seriously considered. High- k gate insulator technology is one of the examples being developed seriously to overcome the problems. In this paper, progress of silicon IC technologies for the past 30 years is described at first. Then, the difficulties of the further downsizing for future are explained in detail. Finally, the efforts to solve difficulties and the possible solutions are described.

Electrical Characteristics for Lu2 O 3 Thin Films Fabricated by E-Beam Deposition Method

Lu 2 O 3 thin films with a high dielectric constant (high k value) deposited on n-Si(100) were investigated. A capacitance equivalent thickness of 1.6 nm with a leakage current density of 1.2 X 10 -3 A/cm 2 (at + 1 V) was obtained for 4.5 nm thick Lu 2 O 3 deposited at room temperature followed by postdeposition annealing (PDA) at 400°C in N 2 . The surface morphology for 8-20 nm thick Lu 2 O 3 films became rough after the PDA process because of the crystallization, whereas the surface of 4.5 nm thick Lu 2 O 3 was smooth even after the PDA process. No frequency dependence in the capacitance-voltage curve was observed, and its relative dielectric constant was 11. The hygroscopic properties of the Lu 2 O 3 thin films seemed to be superior to those of other rare-earth oxide thin films, probably due to Lu 2 O 3 having the largest lattice energy among the rare-earth oxides.

Space-Charge-Limited Currents in La2O3 Thin Films Deposited by E-Beam Evaporation after Low Temperature Dry-Nitrogen Annealing

The electrical characteristics of metal–oxide–semiconductor capacitors with Lanthanum oxide (La2O3) gate dielectrics with 1.1 nm equivalent oxide thickness (EOT) are investigated. La2O3 was deposited by E-beam evaporation on n-Si(100), and annealed at 200°C in dry-nitrogen ex-situ for 5 min. From comparing the leakage currents of as-deposited and annealed oxides, it is shown that the leakage currents of annealed oxide were of two types: low and high leakage currents. The behavior of high leakage currents with applied voltage was similar to that of as-deposited oxide. For the explanation of these two kinds of leakage currents, it is shown that conduction mechanisms strongly related to oxide traps are not responsible for leakage currents, except space-charge-limited current (SCLC). From the applied voltage and temperature dependences of the current of the gate oxide, it is shown that the main conduction mechanisms for the two types of leakage current are SCLC and Schottky conductions at low and high applied voltages, respectively. The dielectric constant obtained from Schottky conduction was 27 and consistent with the C–V result. Based on SCLC theory, trap levels in the oxide band gap composed of both exponential and localized distributions were extracted using the differential method.

Effects of gas phase absorption into Si substrates on plasma doping process

In the low energy plasma doping process, the contribution of not only ionised species but also neutral species to the doping process should be considered. In order to investigate such a contribution, experiments of gas phase doping combined with Ar plasma pre-treatment were carried out. Gas phase impurity absorption should be affected by the Si crystalline disorder caused by the plasma doping. Ar plasma was used to simulate this effect. As a result, significant increase of boron dose from the neutral gas phase was observed when the substrate surface was pre-treated by Ar plasma prior to exposure to neutral B/sub 2/H/sub 6//He gas. The boron was considered to be absorbed in the amorphous layer. Understanding and control of this phenomenon are important for plasma doping technology, in which ion irradiation and absorption of neutral species proceed simultaneously.

Effect of Post-Metallization Annealing on Electrical Characteristics of La2O3 Gate Thin Films

Annealing conditions of a lanthanum oxide (La2O3) metal–insulator–semiconductor (MIS) capacitor were studied in order to optimize the flat-band voltage (VFB). It was confirmed that in the case of using Al electrodes, negative VFB shift was increased by post-deposition annealing (PDA) (before metallization) compared to as-deposited sample, while all other characteristics, such as EOT, leakage current and interface state density, were improved. It was also confirmed that post-metallization annealing (PMA) suppressed the VFB shift. Finally, the combination of PDA and PMA resulted in the recovery of VFB shift with suppression of the decrease of EOT. However, it was confirmed that in the case of using Au electrodes, PMA resulted in a slight negative VFB shift. Judging from these results, it is conceivable that the reaction of the metal with La2O3 exerts a significant influence on the VFB shift.

Effects of Post Dielectric Deposition and Post Metallization Annealing Processes on Metal/Dy2O3/Si(100) Diode Characteristics

Ultra-high vacuum annealing was investigated for Dy2O3 films deposited on Si(100) substrates. The leakage current of the Dy2O3 films deposited at room temperature (RT) was found to be decreased without any increase of the equivalent oxide thickness (EOT) by the in-situ vacuum annealing method compared to that of the conventional rapid thermal annealing (RTA) in O2. The negative flat-band voltage (VFB) shift observed after the in-situ vacuum annealing process was suppressed by increasing the deposition temperature of Dy2O3 on chemically oxidized Si from RT to 250°C. The EOT of 1.1 nm with the leakage current of 0.29 A/cm2 (@VFB+1 V) was obtained for the Dy2O3 film after the air-brake and vacuum annealing, and the EOT of 0.63 nm with 4 A/cm2 (@VFB+1 V) was achieved for the Dy2O3 film with the TaN gate electrode after the post metallization annealing (PMA).

Excellent Current Drivability and Environmental Stability in Room-Temperature-Fabricated Pentacene-Based Organic Field-Effect Transistors With

Low-voltage-operating pentacene-based organic field-effect transistors (OFETs) with HfO₂ gate insulators have been fabricated at room temperature. Despite its thin capacitance equivalent thickness of 3.6 nm, the room-temperature-processed HfO2 gate insulator shows a low leakage current density of 1.2×10^-7 A/cm² at a gate voltage of -2 V. Pentacene films grown on the HfO2 gate insulators have a large grain size and a highly ordered molecular structure due to the appropriate surface properties of the HfO₂ gate insulators. The as-fabricated pentacene-based OFET (W/L=1300 μm/100 μm) with a HfO₂ gate insulator has a low subthreshold swing of 0.13 V/decade, a large ON/OFF current ratio of 9.8×10⁴, and a high hole mobility of 0.34 cm²V^-1s^-1 at an operating voltage of -2 V. Furthermore, the environmental stability in the room-temperature-fabricated pentacene-based OFETs with HfO2 gate insulators was investigated.

{\rm HfO}_{2}

HfOxNy thin-film formation on three-dimensional (3D) Si structures by electron cyclotron resonance (ECR) plasma sputtering was investigated. The sputtering conditions, particularly deposition pressure, and the process of HfOxNy formation, were optimized to prepare uniform films with good electrical properties. It was found that an increase in pressure during HfN deposition from 0.15 to 0.19 Pa improved the step coverage of the HfOxNy film in the sidewall region. Two different processes of HfOxNy thin-film formation using ECR plasma sputtering, namely, HfO2 nitridation and HfN oxidation, were investigated to obtain uniform coverage by optimizing the deposition conditions. However, the interfacial layer (IL) growth was enhanced, which increased equivalent oxide thickness (EOT) in the case of HfO2 nitridation. This problem was mitigated by HfN oxidation even for 3D structures. EOTs of 0.94 and 1.7 nm were obtained for the planar HfOxNy/Si and 3D HfOxNy/Si structures, respectively.