Somaia Sarwat Sylvia

Material Selection for Minimizing Direct Tunneling in Nanowire Transistors

When the physical gate length is reduced to 5 nm, direct channel tunneling dominates the leakage current for both field-effect transistors (FETs) and tunnel FETs. Therefore, a survey of materials in a nanowire geometry is performed to determine their ability to suppress the direct tunnel current through a 5 nm barrier. The materials investigated are InAs, InSb, InP, GaAs, GaN, Si, Ge, and carbon nanotubes. The tunneling effective mass gives the best indication of the relative size of the tunnel currents when comparing two different materials of any type. The indirect-gap materials, Si and Ge, give the largest tunneling masses in the conduction band, and they give the smallest conduction band tunnel currents within the range of diameters considered. Si gives the lowest overall tunnel current for both the conduction and valence bands, and therefore, it is the optimum choice for suppressing tunnel current at the 5 nm scale. A semianalytic approach to calculating tunnel current is demonstrated, which requires considerably less computation than a full-band numerical calculation.

The coherent interlayer resistance of a single, rotated interface between two stacks of AB graphite

The coherent, interlayer resistance of a misoriented, rotated interface between two stacks of AB graphite is determined for a variety of misorientation angles. The quantum-resistance of the ideal AB stack is on the order of 1 to 10 mΩ μm2. For small rotation angles, the coherent interlayer resistance exponentially approaches the ideal quantum resistance at energies away from the charge neutrality point. Over a range of intermediate angles, the resistance increases exponentially with cell size for minimum size unit cells. Larger cell sizes, of similar angles, may not follow this trend. The energy dependence of the interlayer transmission is described.

Doping, Tunnel Barriers, and Cold Carriers in InAs and InSb Nanowire Tunnel Transistors

InAs and InSb nanowire tunnel field-effect transistors require highly degenerate source doping to support the high electric fields in the tunnel region. For a target on-current of 1 μA, the source Fermi energy lies in the range of 0.1-0.22 eV below the valence band edge depending on the material and diameter. Despite the large degeneracy, the devices achieve minimum inverse subthreshold slopes of ~ 30 mV/dec. In the subthreshold, these devices experience both regimes of “voltage-controlled tunneling” and “cold-carrier injection.” The reduction of the inverse subthreshold slope from each of these two processes is quantified. Numerical results based on a discretized eight-band k-p model are compared to analytical WKB theory. The standard WKB theory gives good qualitative agreement with the full-band numerical simulations.

Effect of Random, Discrete Source Dopant Distributions on Nanowire Tunnel FETs

The finite number, random placement, and discrete nature of the dopants in the source of an InAs nanowire tunnel field-effect transistor affect the drive current and the inverse subthreshold slope. The impact of source scattering is negligible, since the current is limited by the interband tunneling. The most significant effect of the discrete dopants is to create variations of the electric fields in the tunnel barrier, which cause variations in the current. The relative variation in the ON current decreases as the average doping density and/or nanowire diameter increases. Results from full self-consistent nonequilibrium Greens function calculations and semiclassical calculations are compared.

The impact of the ring shaped valence band in few-layer iii-vi materials on fet operation

Mexican hat shaped dispersions are relatively common in few-layered two-dimensional materials. In one to four monolayers of the group-ill chalcogenides (GaS, GaSe, InS, InSe) the valence band undergoes a band inversion from parabolic to a Mexican hat dispersion [1]. This Mexican hat dispersion results in a singularity in the density of states at the band edge. This enhances the thermo electric properties, however the effect on field effect transistor performance has not yet been investigated. To evaluate the impact of this ring shaped disperision on FET performance, we use a top of the barrier FET model. The physical gate length, effective oxide thickness and power supply voltage for the simulated devices are 12.8 nm, 0.68nm, and 0.3V respectively, following the low-voltage parameters described by Nikonov and Young [2]. The simulated device is shown in Fig. 1. To model the electrostatic potential along the channel of the device we solve a 2-D Poisson equation over the simulation domain. The density of states and density of modes calculated from the Mexican hat dispersion described in Ref. [I] are shown in Figs. 2 and 3, respectively. The density of modes is used as input for the current calculation. The performance characteristics of the devices are benchmarked using the 15nm node low- voltage criteria defined by Nikonov and Young [2] and compared to other devices.