Sonda Chtourou

Corporate Governance and Earnings Management

This study investigates whether a firms corporate governance practices have an effect on the quality of its publicly released financial information. In particular, we examine the relationship between audit committee and board of directors characteristics and the extent of corporate earnings management as measured by the level of positive and negative discretionary accruals. Using two groups of US firms, one with relatively high and one with relatively low levels of discretionary accruals in the year 1996, we find that earnings management is significantly associated with some of the governance practices by audit committees and boards of directors. For audit committees, income increasing earnings management is negatively associated with a larger proportion of outside members who are not managers in other firms, a clear mandate for overseeing both the financial statements and the external audit, and a committee composed only of independent directors that meets more than twice a year. We also find that short-term stocks options held by non-executive committee members are associated with income increasing earnings management. Income decreasing earnings management is negatively associated with the presence of at least a member with financial expertise and a clear mandate for overseeing both the financial statements and the external audit. For the board of directors, we find less income increasing earnings management in firms whose outside board members have experience as board members with the firm and with other firms. We also find that larger board, the importance of the ownership stakes in the firm held by non-executive directors, and experience as board members seems to reduce income decreasing earnings management. Our results provide evidence that effective boards and audit committees constrain earnings management activities. These findings have implications for regulators, such as the Securities and Exchange Commission (SEC), as they attempt to supervise firms whose financial reporting is in the gray area between legitimacy and outright fraud and where earnings statements reflect the desires of management rather than the underlying financial performance of the company, as pointed out by the Blue Ribbon Committee (1999).

Exploration of Mesh-Based FPGA Architecture: Comparison of 2D and 3D Technologies in Terms of Power, Area and Performance

In this paper, we propose a 2D and 3D interconnect network based on a Mesh-of-Clusters (MoC) topology for the implementation of an efficient Field Programmable Gate Arrays (FPGA) architecture. Proposed MoC-based FPGA architecture presents a new hierarchical Switch Box (SBs) and depopulated intra-cluster interconnect based on the Butterfly-Fat-Tree (BFT) topology. Long routing wires which span multiple SBs in every row and column were used in order to improve performance. By adjusting the percentage of long wire and span, we can design and build 3D high density MoC-based FPGA. To design 3D MoC-based FPGAs, we cut the 2D FPGA into two equal FPGA dies and we adjust the long wire span factor to connect the two dies. Then, these long wire segments are converted as 3D through silicon via (TSV). We present also a design methodology and CAD tools to explore the performance of proposed 2D and 3D MoC-based FPGA architectures in term of power, energy, area and delay. Experimental results with large benchmarks show that with 3D MoC-based FPGA the average gains in terms frequency, energy and area are 23%, 37% and 47% respectively, compared to 2D MoC-based FPGA.

Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires

This paper presents an improved interconnect network for Mesh of Clusters (MoC) Field-Programmable Gate Array (FPGA) architecture. Proposed architecture has a depopulated intra-cluster interconnect with flexible Rents parameter. It presents new multi-levels Switch Box (SB) interconnect which unifies a downward and an upward unidirectional networks based on the Butterfly-Fat-Tree (BFT) topology. To improve the routability of proposed MoC-based FPGA, long routing segments are introduced as a function of channel width with adjustable span. Compared to basic Versatile Place and Route (VPR) Mesh architecture, a saving of 32% of area and 30% of power was achieved with proposed MoC-based architecture. Based on analytical and experimental methods, we identified and explored architecture parameters that control the interconnect flexibility of the proposed MoC-based FPGA such as Rents parameter, cluster size, Look-Up-Table (LUT) size, long wires span and percentage. Experimental results show that architecture with LUT size 4 and Cluster arity 8 is the best trade-off between power consumption and density. It can also be noted that in general long wires span equal to 4 and percentage between 20% and 30% produce most efficient results in terms of density and power.

The effect of interconnect depopulation on FPGA performances in terms of power, area and delay

The interconnect structure in common FPGA architectures is generally designed to maximize logic utilization. A fully populated routing interconnect is simple and provides high flexibility at the cost of power and area overhead. Moreover, the utilization rate of interconnect switches is extremely low. In this paper, we aim to explore new cluster-based mesh FPGA architectures with depopulated routing network. First, we propose a Depopulated FPGA (DFPGA) architecture with depopulated intra-cluster and inter-cluster interconnects. Based on a comparison with a common Mesh architecture, we note that power and area are improved respectively by an average of 23% and 30%. However, these improvements are obtained at the cost of wiring complexity, congestion and low flexibility to route complex circuits. To alleviate those weaknesses, we propose to populate inter-cluster interconnect by using hierarchy. We show experimentally that the second proposed FPGA architecture with Multilevel Switch blocks (MS-FPGA) has a good routability and interesting power consumption and area density compared to the common cluster-based mesh FPGA. Moreover, additional switches used in the hierarchical inter-cluster interconnect of the MSFPGA are compensated with a better flexibility. Unlike DFPGA, MS-FPGA can deal with complex circuits.

Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization

In this paper, we present an improved Mesh of Clusters (MoC) architecture with new hierarchical Switch Box (SB) topology and depopulated intra-cluster interconnect with flexible Rent’s parameter. The aim of this paper is to explore the effect of different architecture parameters like architecture Rent’s, design Rent’s and channel width. Then, we analyze how these factors interact and the way to tune them to satisfy various specific application constraints and quality metrics like power consumption and area. The proposed exploration methodology unifies two procedures which are analytical method based on Rent’s rule modeling and experimental method based on benchmarks circuits implementation. A comparison with VPR mesh architecture shows gains in terms power and area equal respectively to 30% and 32%.

Power consumption analysis for mesh based FPGA

This paper presents the power consumption analysis of two different routing architectures for mesh based FPGAs. The first architecture uses bidirectional Switch Box (SB) implemented using back-to-back tri-state drivers. The second one uses bidirectional SB implemented using tri-states and multiplexers. This paper highlights and experimentally demonstrates the benefit that can be reached by using multiplexers instead of back-to-back tri-state. In fact, total power consumption is reduced by around 23.5% with 0,13 μm technology which provides transistor with low leakage power and realizes 47% power savings with 0,18 μm technology. This benefit is due to a reduction in term of leakage power consumed by routing resource.

Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation

In this study, we propose a three-dimensional (3D) interconnect network implementation based on a modified Mesh-of-Clusters (MoC) topology for FPGA architecture design. Design and experimental setup is developed to demonstrate the improvement in performance, power and area of 2.5D and 3D MoC-based FPGA architecture. MoC starts with a mesh of nodes and builds a separate hierarchical network along each row and column in the mesh. To obtain the optimal MoC programmable interconnect structure with high performance and density, the routing architecture of the 2D MoC-based FPGA is modified to include long routing segments which span multiple switch blocks in every row and column. By adjusting the percentage of long wire and span, we can design and build 2.5D and 3D high density MoC FPGAs. To design 3D MoC-based FPGAs, we cut the 2D MoC FPGA into two equal FPGA dies and we adjust the long wire span factor to connect the two dies. Then, these long wire segments are converted as 3D through silicon via (TSV) technology. To design 2.5D interposer based multi-FPGA architecture, we use the same principle of cuts and we adjust the long wires span to remain within die connections. However, we apply constraints at cutline location to reduce the die to die interposer connections. A 3D physical design CAD for MoC-based FPGA is developed using Global Foundries 130nm technology node modified to use TSV designs from Tezzaron Semiconductor inc. Using our 3D design and simulation tool flow developed for MoC-based FPGA, we demonstrate that the speed, power and area of 3D MoC-based FPGA architecture are improved respectively by 35%, 21% and 47% in comparison to 2D MoC-based FPGA.

On Exploiting Partitioning-Based Placement Approach for Performances Improvement of 3D FPGA

Three-dimensional Field Programmable Gate Arrays (3D FPGAs) represent a viable alternative to overcome challenges of integration complexity in modern embedded systems. Mapping applications into 3D FPGAs requires a set of accompanying suite of Computer-Aided Design (CAD) tools. One of critical issue of a 3D FPGA-based implementation is the quality and efficiency of associated CAD algorithms. In this paper, we are interested to investigate placement algorithms aspect to optimize proposed 3D FPGA performances. In fact, the way we distribute clusters between 3D FPGA layers has an important impact on performances. We present partitioning- based placement algorithm for 3D FPGA. The circuit is first divided into two layers with limited number of inter-layer interconnections, and then placed on individual layers. Placement solution of each layer is then gradually improved using adapted simulated annealing algorithm. We conduct experiments using exploration platform to compare partitioning-based and simulated annealing based placement approaches for proposed 3D FPGA architecture. Exploration results show that using partitioning-based placement algorithm achieves a saving in terms of power consumption, area and performance by an average of 15%, 18% and 10% Unlike DFPGA, MS-FPGA can deal with complex circuits.

Rebuilding synthesized design hierarchy based on instances path names of flattened netlist

Hierarchical representation can greatly simplify many FPGA Computer-Aided Design (CAD) operations such as: design verification, partitioning and placement. In this paper, we propose a hierarchical synthesis environment for Mesh-based FPGA architectures. Our proposed approach uses the flattened netlist resulting from ODIN II tool and reconstructs the hierarchy of the initial Verilog design according to instances names. Results show that reconstructing design hierarchy enables to reduce the number of external nets compared with flattened netlist.

Design of advanced 2D and 3D FPGAs: Architecture-level exploration and algorithm-level optimization

Field Programmable Gate Arrays (FPGAs) have become popular media for the implementation of many digital circuits. The quality of FPGA device is controlled by three factors which are: quality of the FPGA architecture, quality of the Computer-Aided Design (CAD) tools used to map circuits into the FPGA and electrical design of the FPGA. The subject of this paper is the exploration and optimization of cluster-based mesh FPGAs. To conduct this objective, we propose an exploration environment for cluster-based mesh FPGA architectures to explore and improve power consumption, area and performance. We propose also a new 2D cluster-based mesh FPGA architecture using hierarchical interconnect topology and long routing wires. With experimental method, we explore the effect of architecture parameters that control the interconnect flexibility. Results show that long routing wires improve the FPGA flexibility and performance. Nevertheless, as the long wires span increases, their delay also increases and impedes the overall performances. To mitigate the long wire length issues and improve performances, we propose to explore a development methodology of stacked FPGA architecture using 3D technology process. By adjusting the span of long wires, we can design two-tiers 3D cluster-based FPGA with 2 identical 2D functional layers. Moreover, we propose to investigate CAD algorithms aspect to optimize the mapping of application on the 3D FPGA architecture.