Habib Mehrez

Efficient polyphase decomposition of comb decimation filters in /spl Sigma//spl utri/ analog-to-digital converters

A power efficient multirate multistage Comb decimation filter for mono-bit and multi-bit /spl Sigma//spl utri/ A/D converters is presented. Polyphase decomposition in all stages, with high decimation factor in the first stage, is used to significantly reduce the sampling frequency of the Comb filter. Several implementations indicate that proper choice of the first stage decimation factor can considerably improve power consumption, area and maximum sampling frequency. In multibit /spl Sigma//spl utri/ A/Ds, this optimum first stage decimation factor is a function of the input wordlength.

Efficient polyphase decomposition of Comb decimation filters in /spl Sigma//spl Delta/ analog-to-digital converters

A power efficient multi-rate multi-stage Comb decimation filter for mono-bit and multi-bit /spl Sigma//spl Delta/ A/D converters is presented. Polyphase decomposition in all stages, with high decimation factor in the first stage, is used to significantly reduce the sampling frequency of the Comb filter. Several implementations indicate that proper choice of the first stage decimation factor can considerably improve power consumption, area and maximum sampling frequency. In multibit /spl Sigma//spl Delta/ A/Ds, this optimum first stage decimation factor is function of the input wordlength.

A family of redundant multipliers dedicated to fast computation for signal processing

In view of the performance achieved through the use of the redundant addition, it would appear interesting to generalize the redundant notations (Carry Save, Borrow Save). To achieve this we require, as well the addition, a multiplication satisfying these notations. This paper presents the design of a set of multipliers spanning all possible I/O combinations, in redundant and conventional notations. We also describe the associated architectures and details of our method, which is based on parameterizable IP cores. The functions developed offer superior performance over conventional multipliers.

Tree-based Heterogeneous FPGA Architectures: Application Specific Exploration and Optimization

This book presents a new FPGA architecture known as tree-based FPGA architecture, due to its hierarchical nature. This type of architecture has been relatively unexplored despite their better performance and predictable routing behavior, as compared to mesh-based FPGA architectures. In this book, we explore and optimize the tree-based architecture and we evaluate it by comparing it to equivalent mesh-based FPGA architectures.

A fast and low-power distance computation unit dedicated to neural networks, based on redundant arithmetic

This paper presents the design of a fast and low power consumption distance computation unit : /spl Sigma//sub i/(A/sub i/-B/sub i/)/sup 2/. It is dedicated to the digital RBF neural network implementation. The proposed architecture is composed of two parts. The first computes the distance (A/sub i/-B/sub i/)/sup 2/, and the second performs the sum of these distances. It is based on an efficient squarer in redundant arithmetic. Thank to this operator, the distance measure circuits developed offer better performances than those based on classical arithmetic. The average gain is equal to 11% in delay and 18% in power consumption.

Customizable DSP architecture for ASIP core design

We present in this paper a configurable DSP architecture and its associated software framework intended to be used in ASIP core design. This architecture aims to speed up the execution of a well-defined target application and minimize the hardware cost. It is based on a configurable and modular model that makes the most of intrinsic ILP of the application by the use of specialized functional units and VLIW instructions. Implementation results of a complex application, the GSM EFR encoder algorithm, shows the efficiency of the customized architecture.

Implementation of scalable embedded FPGA for SOC

Integrating an embedded FPGA into SoC allows post-fabrication changes. Thanks to their unlimited reconfigurability, eFPGAs are able to implement specific functions, thus improves the systems performance. In this paper the authors present an SRAM-based eFPGA architecture. The authors explore the hardware aspects of the eFPGA including internal structure and external coupling with a VCI interconnect. The authors also focus on the design flow for the implementation and the configuration

Three-Dimensional Integration: A More Than Moore Technology

Three-dimensional integrated circuits (3D-ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture and may facilitate the integration of heterogeneous materials, devices, and signals and offer a promising solution for reducing both silicon footprint and interconnect length without shrinking the transistors. However, before these advantages can be realized, key technology and CAD challenges of 3D-ICs must be addressed. More specifically, the process required to build circuits with multiple layers of active devices and CAD tools used for design and validation of such circuits. Several such methodologies and CAD tools associated with the design fabrication of 3-D ICs are discussed in this chapter. Few successful 3D-IC design methods and CAD tools and benefits of applying 3D design to the future reconfigurable systems are also discussed in this chapter.

Inter-FPGA routing environment for performance exploration of multi-FPGA systems

Multi-FPGA platforms are a popular choice today for complex system prototyping because they offer high execution speed, low cost, and real world testing experience. However, performance of multi-FPGA based systems is severely affected by widening logic to I/O gap in FPGAs. In order to address the performance issue, in this work, we propose an exploration and optimization flow for multi-FPGA based prototyping that gives an end-to-end experience starting from benchmark generation to optimized inter- FPGA routing. Using generic tools of the flow, ten large benchmarks are generated. Then, through a generic novel inter-FPGA routing environment, effect of variation of number of FPGAs as well as number of inter-FPGA tracks on the performance of a target design is explored. For performance exploration and optimization, five different FPGA boards are utilized where number of FPGAs on board are varied from two to six. Moreover, for each board four different inter-FPGA track combinations are used. Experimental results reveal that multi-FPGA boards with inter-FPGA tracks corresponding optimally to the cut net requirements of benchmarks under consideration give best frequency results. Furthermore, frequency comparison between different boards shows that FPGA board with six FPGAs gives, on average, best frequency results. Finally, we also perform frequency-price analysis which shows that board with four FPGAs gives better frequency-price tradeoff as compared to other FPGA boards under consideration.

Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancy

The technological evolution involves a higher number of physical defects in circuits after manufacturing. One of the future challenge is to find a way to use a maximum of defected manufactured circuits. In this paper, multiple techniques are proposed to avoid defects in the cluster local interconnect of a SRAM-based Mesh of Clusters FPGA. Using defect tolerance, area and timing metrics, two previous hardware redundancy strategies are evaluated on the Mesh of Clusters architecture : Fine Grain Redundancy (FGR) and Improved Fine Grain Redundancy (IFGR). We show that using these techniques on a cluster of a Mesh of Clusters architecture permits to tolerate 8 times more defects than on an industrial Mesh FPGA with a low area overhead (-6% for FGR and 22% for IFGR) and a low increase of Critical Path Delay (CPD)(6% for FGR and 2% for IFGR). We also proposed three new redundancy strategies using spare resources : Distributed Feedbacks (DF) for crossbar down, Adapted Fine Grain Redundancy (AFGR) to avoid defective multiplexers and Upward Redundant Multiplexer (URM) for the crossbar up. Compared to the Mesh of Clusters architecture without defect tolerance techniques, the best trade off between defect tolerance (36.4%), area overhead (11.56%) and CPD (+7.46%) is obtained using AFGR. Using the other methods permits to considerably limit the area overhead (10.4% with URM) with a lesser number of defective elements bypassed (18% max).