Song Chai

Design and simulation of a torus structure and route algorithm for network on chip

With the development of VDSM, the rising scale and complexity of system-on-chip induce significant communication challenges in bus based architectures. The interconnect delay and unpredictable delay are gradually becoming the bottle neck of increasing complexity for on-chip systems. Current NOC (network on chip) provides an effective solution to these communication problems. In this paper, we study the Torus topology and bring forward a structure for NOC. Besides, we propose a dead-lock and live-lock free route algorithm. During the simulation, we found that our structure and algorithm are superior in hotspot traffic pattern. Furthermore, latency time and throughput of Torus NOC we designed have been tremendously improved comparing with XY Mesh structure.

A NoC Simulation and Verification Platform Based on SystemC

This paper presents a NoC (network-on-chip) simulation and verification platform (NSVP) based on SystemC. A general NoC node structure is first realized under SystemC, and then connected to form the network. NSVP supports an arbitrary size of mesh and torus topology, and adopts two classic routing algorithms - XY and TXY as the routing algorithm. Users also can develop their own network topology and routing algorithm by modifying the corresponding modules. Then they can verify their design by loading different network traffic patterns to run the simulation. NSVP provides a fast and convenient platform for researching and verification of NoC architecture and routing algorithm.

Lottery Router: A Customized Arbitral Priority NOC Router

For the different communications of specific NOC (network on chip) applications, this paper proposes a customized arbitral priority NOC router. This router uses the arbitral mechanism based on lottery algorithm instead of the RR (round robin) algorithm, which is widely used in the arbiter of current NOC routers. The arbitral priority of lottery router can be customized by users according to the communication cases among IPs in NOC. Through the analysis of different priority input ports competing for the same output port, it is illustrated that the lottery mechanism distinguish different priorities and guarantee the response to the high priority port. This paper uses SystemC to implement the router and build a NOC based on the 2D mesh to simulate and compare the performance of lottery router with RR router in average delay and the network resources utilization.

A Comparison of Genetic Algorithm, Particle Swarm Optimization and Simulated Annealing in Real-Time Task Scheduling on CMP

Real-time task schedule problem in Chip-Multiprocessor (CMP) receives wide attention in recent years. It is partly because the increasing demand for CMP solutions call for better schedule algorithm to exploit the full potential of hardware, and partly because of the complexity of schedule problem, which itself is an NP-hard problem. To address this task schedule problem, various of heuristics have been studied, among which, Genetic Algorithm (GA), Particle Swarm Optimization (PSO) and Simulated Annealing (SA) are the most popular ones. In this paper, we implement these 3 schedule heuristics, and compare their performance under the context of real-time tasks scheduling on CMP. According to the results of our intensive simulations, PSO has the best fitness optimization of these 3 algorithms, and SA is the most efficient algorithm.

A Genetic Algorithm for Task Scheduling on NoC Using FDH Cross Efficiency

A CrosFDH-GA algorithm is proposed for the task scheduling problem on the NoC-based MPSoC regarding the multicriterion optimization. First of all, four common criterions, namely, makespan, data routing energy, average link load, and workload balance, are extracted from the task scheduling problem on NoC and are used to construct the DEA DMU model. Then the FDH analysis is applied to the problem, and a FDH cross efficiency formulation is derived for evaluating the relative advantage among schedule solutions. Finally, we introduce the DEA approach to the genetic algorithm and propose a CrosFDH-GA scheduling algorithm to find the most efficient schedule solution for a given scheduling problem. The simulation results show that our FDH cross efficiency formulation effectively evaluates the performance of schedule solutions. By conducting comparative simulations, our CrosFDH-GA proposal produces more metrics-balanced schedule solution than other multicriterion algorithms.

Minimizing virtual channel buffer for Network-on-Chip

A novel method to optimize the number of virtual channel buffers is proposed in this paper. More precisely, given the application task graph of a specific application, an ACO (Ant Colony Optimization) algorithm is used during the mapping of tasks to the NoC (Network-on-Chip) such that the number of virtual channel buffers is minimized. The benefit of our method is evaluated by simulation and the simulation results show that our method can achieve 33% reduction in the number of virtual channel buffers compared to the state-of-art method.