Yubai Li

A New CDMA Encoding/Decoding Method for on-Chip Communication Network

As a high performance on-chip communication method, the code division multiple access (CDMA) technique has recently been applied to networks on chip (NoCs). We propose a new standard-basis-based encoding/decoding method to leverage the performance and cost of CDMA NoCs in area, power assumption, and network throughput. In the transmitter module, source data from different senders are separately encoded with an orthogonal code of a standard basis and these coded data are mixed together by an XOR operation. Then, the sums of data can be transmitted to their destinations through the on-chip communication infrastructure. In the receiver module, a sequence of chips is retrieved by taking an AND operation between the sums of data and the corresponding orthogonal code. After a simple accumulation of these chips, original data can be reconstructed. We implement our encoding/decoding method and apply it to a CDMA NoC with a star topology. Compared with the state-of-the-art Walsh-code-based (WB) encoding/decoding technique, our method achieves up to 67.46% power saving and 81.24% area saving together with decrease of 30%-50% encoding/decoding latency. Moreover, the CDMA NoC with different sizes applying our encoding/decoding method gains power saving, area saving, and maximal throughput improvement up to 20.25%, 22.91%, and 103.26%, respectively, than the WB CDMA NoC.

System-level Buffer Allocation for Application Specific Network-on-chip with Wormhole Routing

Abstract A novel buffer allocation algorithm that can be used to customize the router design in application-specific Network-on-Chip (NoC) is proposed. More precisely, according to the target application and the total budget of the available buffer resources, the proposed method automatically assigns the buffer size for each input port in different routers across the NoC, such that the overall performance is maximized. Indeed, the experimental results show that while the proposed method in this paper is used, significant performance improvements can be achieved compared to the state-the-of-art buffer allocation methods. It also allows our NoC to achieve the same performance level as the NoC which assigns buffer resources by using the state-of-art buffer allocation methods but using fewer buffer resources.

An analytical model for Network-on-Chip with finite input buffer

An analytical model is proposed for input buffer router architecture Network-on-Chip (NoC) with finite size buffers. The model is developed based on M/G/1/K queuing theory and takes into consideration the restriction of buffer sizes in NoC. It analyzes the packet’s sojourn time in each buffer and calculates the packets average latency in NoC The validity of the model is verified through simulation. By comparing our analytical outcomes to the simulation results, we show that the proposed model successfully captures the performance characteristics of NoC, which provides an efficient performance analysis tool for NoC design.

A High-Level Thermal Model-Based Task Mapping for CMPs in Dark-Silicon Era

The chip multiprocessor (CMP) thermal issue impacting the system reliability and cooling cost has become a limiting factor for chip scaling and attracted growing attentions in the dark-silicon era. We propose a thermal-aware thread-to-core mapping method for CMPs under the dark-silicon constraint. We first propose a high-level spatial-temporal information-based thermal model to capture the relationship between the mapping result and the system thermal distribution. Then, we develop a thermal-aware mapping algorithm, which can automatically assign threads to proper cores based on the proposed model. Finally, we evaluate our method through simulations. Compared with three other mapping methods, namely, random, network-on-chip (NoC)-sprinting and round-robin, our thermal-priority design decreases the peak temperature by up to 4.31 K while showing good communication performance (34.7% of improvement against random and 50.3% against NoC sprinting, and only 6.3% of degradation against round robin); and our latency-priority design achieves the best communication performance with an improvement up to 62.6% and a satisfactory thermal profile.

A Genetic Algorithm for Task Scheduling on NoC Using FDH Cross Efficiency

A CrosFDH-GA algorithm is proposed for the task scheduling problem on the NoC-based MPSoC regarding the multicriterion optimization. First of all, four common criterions, namely, makespan, data routing energy, average link load, and workload balance, are extracted from the task scheduling problem on NoC and are used to construct the DEA DMU model. Then the FDH analysis is applied to the problem, and a FDH cross efficiency formulation is derived for evaluating the relative advantage among schedule solutions. Finally, we introduce the DEA approach to the genetic algorithm and propose a CrosFDH-GA scheduling algorithm to find the most efficient schedule solution for a given scheduling problem. The simulation results show that our FDH cross efficiency formulation effectively evaluates the performance of schedule solutions. By conducting comparative simulations, our CrosFDH-GA proposal produces more metrics-balanced schedule solution than other multicriterion algorithms.

A Thermal Balance Oriented Task Mapping for CMPs

CMP (Chip Multi Processors) has been concerned and applied in more and more fields. With the technical progress in semiconductor manufacturing, the focus/research on on-chip power density and heat generation of the chips are increasing. The heat distribution of the chip heavily affects its reliability. In this article a heat-balancing task mapping algorithm is proposed to optimize the heat distribution and ensure the reliability of CMP. First, the thermal distribution of CMP is analyzed by what. Then, based on above analysis, a cost function based on usage and location of on-chip processors is proposed. Finally, a mapping algorithm based on above cost function is developed to assign threads to cores while running applications with the min-cost principle dynamically. The simulation results revel that the heat-balancing algorithm proposed effectively optimizes heat distribution and ensures computational performance either.

A New Parallel CODEC Technique for CDMA NoCs

Code division multiple access (CDMA) network-on-chip (NoC) has been proposed for many-core systems due to its data transfer parallelism over communication channels. Consequently, coder–decoder (CODEC) module, which greatly impacts the performance of CDMA NoCs, attracted growing attention in recent years. In this paper, we propose a new parallel CODEC technique for CDMA NoCs. In general, by using a few simple logic circuits with small penalties in area and power, our new parallel (NPC) CODEC can execute the encoding/decoding process in parallel and thus reduce the data transfer latency. To reveal the benefits of our method for on-chip communication, we apply our NPC to CDMA NoCs and perform extensive experiments. From the results, we can find that our method outperforms existing parallel CODECs, such as Walsh-based parallel CODEC (WPC) and overloaded parallel CODEC (OPC). Specifically, it improves the critical point of communication latency (7.3% over WPC and 13.5% over OPC), reduces packet latency jitter by about 17.3% (against WPC) and 71.6% (against OPC), and improves energy efficiency by up to 41.2% (against WPC) and 59.2% (against OPC).

A PSO-Based Layout Method for GNSS Pseudolite System

In order to improve the user positioning accuracy in GNSS (Global Navigation Satellite System) pseudolite system, we propose a PSO (Particle Swarm Optimization)-based method to optimize the pseudolite layout in this paper. In detail, given the pseudolite layout information, we calculate the system GDOP (Geometric Dilution of Precision) and then minimize it by using a PSO-based algorithm with N particles. Here the first particle indicates the classical layout under the given scenario and the other particles separately represent N-1 randomly generated layouts. In each iteration of our PSO-based algorithm, these particles move to a direction to reduce the GDOP value. After several iterations, the GDOP value can be minimized and the optimal pseudolite layout is found out as well. To evaluate the merits of our method, we perform some experiments. The experimental results show that compared to the classical pseudolite layout, our method can reduce the GDOP by 13.4%. This, with no doubt, improves the user positioning accuracy. For example, when the pseudo-range error is about 1%, the user positioning accuracy in our optimized layout can be improved by 12.4% against the classical layout.

ACO-Based Thermal-Aware Thread-to-Core Mapping for Dark-Silicon-Constrained CMPs

The limitation on thermal budget in chip multiprocessor (CMP) results in a fraction of inactive silicon regions called dark silicon, which significantly impacts the system performance. In this paper, we propose a thread-to-core mapping method for dark-silicon-constrained CMPs to address their thermal issue. We first propose a thermal prediction model to forecast CMP temperature after the CMP executes a forthcoming application. Then, we develop an ant colony optimization-based algorithm to conduct the thread-to-core mapping process, such that the CMP peak temperature is minimized and, consequently, the probability of triggering CMP dynamic thermal management is decreased. Finally, we evaluate our method and compare it with the baseline (a standard Linux scheduler) and other existing methods (NoC-Sprinting, DaSiM mapping, and TP mapping). The simulation results show that our method gains good thermal profile and computational performance, and performs well with chip scaling. Specifically, it eliminates all thermal emergency time, outperforming all other methods, and gains million instructions per second improvement up to 12.9% against the baseline.

A System-level Bandwidth Design Method for Wormhole Network-on-Chip

ABSTRACT To improve the Network-on-Chip (NoC) performance, we propose a system-level bandwidth design method customising the bandwidths of the NoC links. In details, we first built a mathematical model to catch the relationship between the NoC commutation latency and the NoC link bandwidth, and then develop a bandwidth allocation algorithm to automatically optimise the bandwidth for each NoC link. The experimental results show that our bandwidth-customising method improves the NoC performance compared to the traditional uniform bandwidth allocation method. Besides, it can also make our NoC to achieve the same communication performance level as the uniform bandwidth NoC but using fewer bandwidth resources, which is beneficial to save the NoC area and power.