Song Qingwen

Effect of re-oxidation annealing process on the SiO2/SiC interface characteristics

The effect of the different re-oxidation annealing (ROA) processes on the SiO2/SiC interface characteristics has been investigated. With different annealing processes, the flat band voltage, effective dielectric charge density and interface trap density are obtained from the capacitance—voltage curves. It is found that the lowest interface trap density is obtained by the wet-oxidation annealing process at 1050 °C for 30 min, while a large number of effective dielectric charges are generated. The components at the SiO2/SiC interface are analyzed by X-ray photoelectron spectroscopy (XPS) testing. It is found that the effective dielectric charges are generated due to the existence of the C and H atoms in the wet-oxidation annealing process.

Investigation of a 4H—SiC metal—insulation—semiconductor structure with an Al2O3/SiO2 stacked dielectric

Atomic layer deposited (ALD) Al2O3/dry-oxidized ultrathin SiO2 films as a high-k gate dielectric grown on 8° off-axis 4H—SiC (0001) epitaxial wafers are investigated in this paper. The metal—insulation—semiconductor (MIS) capacitors, respectively with different gate dielectric stacks (Al2O3/SiO2, Al2O3, and SiO2) are fabricated and compared with each other. The I—V measurements show that the Al2O3/SiO2 stack has a high breakdown field (≥12 MV/cm) comparable to SiO2, and a relatively low gate leakage current of 1 × 10−7 A/cm2 at an electric field of 4 MV/cm comparable to Al2O3. The 1-MHz high frequency C—V measurements exhibit that the Al2O3/SiO2 stack has a smaller positive flat-band voltage shift and hysteresis voltage, indicating a less effective charge and slow-trap density near the interface.

Investigation of surface morphology and ion activation of aluminium implanted 4H-SiC

Multiple-energy aluminium (Al+) implantation into 4H-SiC (0001) epilayer and activation anneal with a graphite encapsulation layer were investigated in this paper. Measurements showed that the implanted Al+ box doping profile was formed and a high ion activation ratio of 78% was achieved by 40 min annealing at 1600°C using a horizontal chemical vapor deposition (CVD) reactor. The step bunching effect associated with the high temperature post implantation activation annealing (PIA) process was dramatically suppressed by using the graphite encapsulation layer. And a flat and smooth surface with a small average surface roughness (RMS) value of around 1.16 nm was achieved for the implanted 4H-SiC after the PIA process. It was demonstrated that this surface protection technique is a quite effective process for 4H-SiC power devices fabrication.

Investigation of current transport parameters of Ti/4H-SiC MPS diode with inhomogeneous barrier

The current transport parameters of 4H-SiC merged PiN Schottky (MPS) diode are investigated in a temperature range of 300–520 K. Evaluation of the experimental current–voltage (I—V) data reveals the decrease in Schottky barrier height Φb but an increase in ideality factor n, with temperature decreasing, which suggests the presence of an inhomogeneous Schottky barrier. The current transport behaviours are analysed in detail using the Tungs model and the effective area of the low barrier patches is extracted. It is found that small low barrier patches, making only 4.3% of the total contact, may significantly influence the device electrical characteristics due to the fact that a barrier height of 0.968 eV is much lower than the average barrier height 1.39 eV. This shows that ion implantation in the Schottky contact region of MPS structure may result in a poor Ti/4H-SiC interface quality. In addition, the temperature dependence of the specific on-resistance (Ron—sp), T2.14, is determined between 300 K and 520 K, which is similar to that predicted by a reduction in electron mobility.

Influence of geometrical parameters on the behaviour of SiC merged PiN Schottky rectifiers with junction termination extension

This paper investigates the behaviours of 4H–SiC merged PiN Schottky (MPS) rectifiers with junction termination extension (JTE) by extensive numerical simulations. The simulated results show that the present model matches the experimental data very well. The influences of the JTE design parameters such as the doping concentration and length of the JTE on the breakdown characteristics are discussed in detail. Then the temperature sensitivity of the forward behaviour is studied in terms of the different designs of 4H–SiC MPS with JTE, which provides a particularly useful guideline for the optimal design of MPS rectifiers with JTE.

Interface annealing characterization of Ti/Al/Au ohmic contacts to p-type 4H-SiC*

Ti/Al/Au ohmic contacts to p-type 4H-SiC with different Ti composition are reported. The contact with high Ti content yields a lower specific contact resistivity (ρC) of 6.4×10-5Ωcm2, compared with the low-Ti contained contact. The annealed surface morphology and phase products for these contacts are examined by Scanning Electron Microscope (SEM) and X-ray diffraction (XRD) spectra, respectively. These results reveal that rich Ti prevents the large agglomerate grains from the liquid Al during annealing, which is beneficial for interfacial reaction and formation of the ohmic contact.Ti/Al/Au ohmic contacts to p-type 4H-SiC in terms of a different annealing time and Ti composition are reported. At 1050 °C, proper increase in annealing time plays a critical role in the Schottky to ohmic contact conversion. With the optimized annealing time, the contact with a high Ti content yields a lower specific contact resistivity (ρc) of 6.4 × 10−5 Ωcm2 compared with the low-Ti contact. The annealed surface morphology and phase resultants were examined by scanning electron microscopy (SEM) and X-ray diffraction (XRD), respectively. For the better ohmic contact, element distribution and chemical states were qualitatively identified by X-ray photoelectron spectroscopy (XPS) depth analysis. In particular, the presence of C and a Si-related phase was discussed and associated with the change in the surface status of the as-grown epilayer of 4H-SiC during annealing. The results reveal that the out-diffused C and Si atoms, with an approximate atomic ratio of 1 : 1 in the contact layer, can combine to form an amorphous Si–C state. The polycrystalline graphite instead of an unreacted C cluster in the whole alloyed structure and an extra nanosize graphite flake on the outermost surface of the annealed contact were confirmed by Raman spectroscopy.

The fabrication and characterization of 4H?SiC power UMOSFETs

The fabrication of 4H—SiC vertical trench-gate metal-oxide-semiconductor field-effect transistors (UMOSFETs) is reported in this paper. The device has a 15-μm thick drift layer with 3×1015 cm−3 N-type doping concentration and a 3.1-μm channel length. The measured on-state source—drain current density is 65.4 A/cm2 at Vg = 40 V and VDS = 15 V. The measured threshold voltage (Vth) is 5.5 V by linear extrapolation from the transfer characteristics. A specific on-resistance (Rsp-on) is 181 mΩcm2 at Vg = 40 V and a blocking voltage (BV) is 880 V (IDS = 100 μA@880V) at Vg = 0 V.

Simulation study of a mixed terminal structure for 4H-SiC merged PiN/Schottky diode ∗

In this paper, a mixed terminal structure for the 4H-SiC merged PiN/Schottky diode (MPS) is investigated, which is a combination of a field plate, a junction termination extension and floating limiting rings. Optimization is performed on the terminal structure by using the ISE-TCAD. Further analysis shows that this structure can greatly reduce the sensitivity of the breakdown voltage to the doping concentration and can effectively suppress the effect of the interface charge compared with the structure of the junction termination extension. At the same time, the 4H-SiC MPS with this termination structure can reach a high and stable breakdown voltage.

Energy-band alignment of atomic layer deposited（HfO2）x（Al2O3）1-x gate dielectrics on 4H-SiC

We study a series of (HfO2)x(Al2O3)1 − x /4H-SiC MOS capacitors. It is shown that the conduction band offset of HfO2 is 0.5 eV and the conduction band offset of HfAlO is 1.11–1.72 eV. The conduction band offsets of (HfO2)x(Al2O3)1 − x are increased with the increase of the Al composition, and the (HfO2)x(Al2O3)1 − x offer acceptable barrier heights (> 1 eV) for both electrons and holes. With a higher conduction band offset, (HfO2)x(Al2O3)1 − x/4H-SiC MOS capacitors result in a ~ 3 orders of magnitude lower gate leakage current at an effective electric field of 15 MV/cm and roughly the same effective breakdown field of ~ 25 MV/cm compared to HfO2. Considering the tradeoff among the band gap, the band offset, and the dielectric constant, we conclude that the optimum Al2O3 concentration is about 30% for an alternative gate dielectric in 4H-SiC power MOS-based transistors.

Low specific contact resistance on epitaxial p-type 4H-SiC with a step-bunching surface*

This paper reports the performances of Ti/Al based ohmic contacts fabricated on highly doped p-type 4H-SiC epitaxial layer which has a severe step-bunching surface. Different contact schemes are investigated based on the Al:Ti composition with no more than 50 at.% Al. The specific contact resistance (SCR) is obtained to be as low as 2.6 × 10−6 Ωcm2 for the bilayered Ti(100 nm)/Al(100 nm) contact treated with 3 min rapid thermal annealing (RTA) at 1000 °C. The microstructure analyses examined by physical and chemical characterization techniques reveal an alloy-assisted ohmic contact formation mechanism, i.e., a high degree of alloying plays a decisive role in forming the interfacial ternary Ti3SiC2 dominating the ohmic behavior of the Ti/Al based contact. Furthermore, a globally covered Ti3SiC2 layer with (0001)-oriented texture can be formed, regardless of the surface step bunching as well as its structural evolution during the metallization annealing.