Tang Xiaoyan

Temperature-dependent characteristics of 4H—SiC junction barrier Schottky diodes

Nowadays, almost all power electronic converter systems use Si-based power semiconductor switches. The performance of these switches is approaching the theoretical limit of the Si material. Another material with superior properties as compared with Si is silicon carbide (SiC), which is a promising candidate for use in the next generation of power devices, especially for high-voltage or high-temperature applications. Several papers have compared the Sibased with SiC-based power electronic devices and given the relative merits of wide band gap semiconductors, like SiC for high-voltage or high-temperature applications.[1−3] The 4H–SiC Schottky barrier diodes (SBDs) have been proved to have great potential in power applications because of their low conduction loss and fast switching speed. One major issue of the SBD is its high reverse leakage current, especially at elevated temperatures. The junction barrier Schottky (JBS) diode is proposed for it offers Schottky-like onstate and fast switching characteristics, while the offstate characteristics have a low leakage current similar to that of the PiN diode. However, when temperature rises, the electrical parameters and the conduction mechanism of the metal-semiconductor (MS) interface change. To understand the influence of variation of temperature on the characteristics of 4H–SiC JBS diodes, temperature variation measurements were carried out. Furthermore, current–voltage (I–V ) and reverse recovery characteristics are discussed in this paper. Moreover, the ideality factor, barrier height, series resistance, reverse recovery time, and peak reverse voltage were calculated and analysed.The current—voltage characteristics of 4H—SiC junction barrier Schottky (JBS) diodes terminated by an offset field plate have been measured in the temperature range of 25–300 °C. An experimental barrier height value of about 0.5 eV is obtained for the Ti/4H—SiC JBS diodes at room temperature. A decrease in the experimental barrier height and an increase in the ideality factor with decreasing temperature are shown. Reverse recovery testing also shows the temperature dependence of the peak recovery current density and the reverse recovery time. Finally, a discussion of reducing the reverse recovery time is presented.

Effect of re-oxidation annealing process on the SiO2/SiC interface characteristics

The effect of the different re-oxidation annealing (ROA) processes on the SiO2/SiC interface characteristics has been investigated. With different annealing processes, the flat band voltage, effective dielectric charge density and interface trap density are obtained from the capacitance—voltage curves. It is found that the lowest interface trap density is obtained by the wet-oxidation annealing process at 1050 °C for 30 min, while a large number of effective dielectric charges are generated. The components at the SiO2/SiC interface are analyzed by X-ray photoelectron spectroscopy (XPS) testing. It is found that the effective dielectric charges are generated due to the existence of the C and H atoms in the wet-oxidation annealing process.

Investigation of a 4H—SiC metal—insulation—semiconductor structure with an Al2O3/SiO2 stacked dielectric

Atomic layer deposited (ALD) Al2O3/dry-oxidized ultrathin SiO2 films as a high-k gate dielectric grown on 8° off-axis 4H—SiC (0001) epitaxial wafers are investigated in this paper. The metal—insulation—semiconductor (MIS) capacitors, respectively with different gate dielectric stacks (Al2O3/SiO2, Al2O3, and SiO2) are fabricated and compared with each other. The I—V measurements show that the Al2O3/SiO2 stack has a high breakdown field (≥12 MV/cm) comparable to SiO2, and a relatively low gate leakage current of 1 × 10−7 A/cm2 at an electric field of 4 MV/cm comparable to Al2O3. The 1-MHz high frequency C—V measurements exhibit that the Al2O3/SiO2 stack has a smaller positive flat-band voltage shift and hysteresis voltage, indicating a less effective charge and slow-trap density near the interface.

a DC-DC boost converter based on SiC MOSFET and SiC SBD

Power devices based upon silicon technology are rapidly approaching their theoretical limits of performance. Consequently, it will be necessary to develop devices from other materials in the future in order to reduce power losses in high frequency systems and in order to achieve high efficiencies. This paper presents a DC-DC boost converter based on SiC MOSFET and SiC Schottky Barrier Diode(SBD). This study focuses on demonstrating the capability of a DC/DC boost converter based on SiC devices in the applications at high switch frequency and high temperature operation. The simulation of the DC-DC boost converter is performed with the ISE-TCAD. The simulation results show that a switching frequency of 20 kHz, an output voltage of 500V and the output voltage ripples of 1%. In the steady state of the 20 kHz DC-DC boost converter simulation, the input power is 1248W, the output power is 1200W and the efficiency is as high as 96.1%.

Investigation of surface morphology and ion activation of aluminium implanted 4H-SiC

Multiple-energy aluminium (Al+) implantation into 4H-SiC (0001) epilayer and activation anneal with a graphite encapsulation layer were investigated in this paper. Measurements showed that the implanted Al+ box doping profile was formed and a high ion activation ratio of 78% was achieved by 40 min annealing at 1600°C using a horizontal chemical vapor deposition (CVD) reactor. The step bunching effect associated with the high temperature post implantation activation annealing (PIA) process was dramatically suppressed by using the graphite encapsulation layer. And a flat and smooth surface with a small average surface roughness (RMS) value of around 1.16 nm was achieved for the implanted 4H-SiC after the PIA process. It was demonstrated that this surface protection technique is a quite effective process for 4H-SiC power devices fabrication.

Investigation of current transport parameters of Ti/4H-SiC MPS diode with inhomogeneous barrier

The current transport parameters of 4H-SiC merged PiN Schottky (MPS) diode are investigated in a temperature range of 300–520 K. Evaluation of the experimental current–voltage (I—V) data reveals the decrease in Schottky barrier height Φb but an increase in ideality factor n, with temperature decreasing, which suggests the presence of an inhomogeneous Schottky barrier. The current transport behaviours are analysed in detail using the Tungs model and the effective area of the low barrier patches is extracted. It is found that small low barrier patches, making only 4.3% of the total contact, may significantly influence the device electrical characteristics due to the fact that a barrier height of 0.968 eV is much lower than the average barrier height 1.39 eV. This shows that ion implantation in the Schottky contact region of MPS structure may result in a poor Ti/4H-SiC interface quality. In addition, the temperature dependence of the specific on-resistance (Ron—sp), T2.14, is determined between 300 K and 520 K, which is similar to that predicted by a reduction in electron mobility.

Interface annealing characterization of Ti/Al/Au ohmic contacts to p-type 4H-SiC*

Ti/Al/Au ohmic contacts to p-type 4H-SiC with different Ti composition are reported. The contact with high Ti content yields a lower specific contact resistivity (ρC) of 6.4×10-5Ωcm2, compared with the low-Ti contained contact. The annealed surface morphology and phase products for these contacts are examined by Scanning Electron Microscope (SEM) and X-ray diffraction (XRD) spectra, respectively. These results reveal that rich Ti prevents the large agglomerate grains from the liquid Al during annealing, which is beneficial for interfacial reaction and formation of the ohmic contact.Ti/Al/Au ohmic contacts to p-type 4H-SiC in terms of a different annealing time and Ti composition are reported. At 1050 °C, proper increase in annealing time plays a critical role in the Schottky to ohmic contact conversion. With the optimized annealing time, the contact with a high Ti content yields a lower specific contact resistivity (ρc) of 6.4 × 10−5 Ωcm2 compared with the low-Ti contact. The annealed surface morphology and phase resultants were examined by scanning electron microscopy (SEM) and X-ray diffraction (XRD), respectively. For the better ohmic contact, element distribution and chemical states were qualitatively identified by X-ray photoelectron spectroscopy (XPS) depth analysis. In particular, the presence of C and a Si-related phase was discussed and associated with the change in the surface status of the as-grown epilayer of 4H-SiC during annealing. The results reveal that the out-diffused C and Si atoms, with an approximate atomic ratio of 1 : 1 in the contact layer, can combine to form an amorphous Si–C state. The polycrystalline graphite instead of an unreacted C cluster in the whole alloyed structure and an extra nanosize graphite flake on the outermost surface of the annealed contact were confirmed by Raman spectroscopy.

The fabrication and characterization of 4H?SiC power UMOSFETs

The fabrication of 4H—SiC vertical trench-gate metal-oxide-semiconductor field-effect transistors (UMOSFETs) is reported in this paper. The device has a 15-μm thick drift layer with 3×1015 cm−3 N-type doping concentration and a 3.1-μm channel length. The measured on-state source—drain current density is 65.4 A/cm2 at Vg = 40 V and VDS = 15 V. The measured threshold voltage (Vth) is 5.5 V by linear extrapolation from the transfer characteristics. A specific on-resistance (Rsp-on) is 181 mΩcm2 at Vg = 40 V and a blocking voltage (BV) is 880 V (IDS = 100 μA@880V) at Vg = 0 V.

Methods for Thickness Determination of SiC Homoepilayers by Using Infrared Reflectance Spectroscopy

Infrared reflectance spectra have been widely used to measure layer thickness based either on calculation or on curve fitting, and two traditional methods for thickness determination have been studied. Considering the disadvantages of those two methods, we propose a new fitting model based on the fitting of the fringe order difference. In comparison with the measured results, the new fitting model shows its superiority not only for its stable and accurate results which have great agreement with the results from SEM, but also for its simple and quick fitting process.

Fabrication of Thin Graphene Layers on a Stacked 6H-SiC Surface in a Graphite Enclosure

Thin and homogeneous epitaxial graphene (EG) layers on a 6H-SiC (000) substrate are fabricated and they cover the whole substrate (10 × 10 mm2). The sample surface is capped by another 6H-SiC (000) wafer in a graphite enclosure to form a relatively high Si partial pressure between them, which significantly reduces the extremely high growth rate of EG. The structure and morphology of the EG layers are investigated by Raman spectroscopy, atomic force microscopy and field-emission scanning electronic microscopy. The results are compared with an uncapped sample surface, and reveal the obvious existence of ridges on the surface of the EG, and show that capping is indeed beneficial to obtain homogeneous graphene.