Songlin Feng

A Low-Power Contrast Enhancement Algorithm Using Histogram Segmentation and Circuit Implementation for AMOLED Applications

A low-power contrast enhancement algorithm is proposed for active-matrix organic light-emitting diode (AMOLED) applications in this paper. Compared with the conventional contrast enhancement on global images, the proposed contrast enhancement has been implemented for each histogram segment, respectively, which is better for local contrast. An effective power reduction method to conserve local details is also presented based on the histogram segmentation. Moreover, a self-adaptation power reduction mechanism is further employed to achieve the tradeoff between the image quality and the power consumption for videos. Finally, the algorithm has been implemented on a FPGA with a 2.8-in AMOLED panel. The simulation and experimental results demonstrate that power consumption is reduced by 30%-40% using the algorithm, while keeping a good image quality.

Optimization of the Transient Feature Analysis for Graphene Chemical Vapor Sensors: A Comprehensive Study

Graphene is very attractive for chemical vapor sensor applications due to its atomically thin structure and unique electronic properties. In this paper, a comprehensive study of transient feature analysis is carried out to optimize the discrimination capability of graphene chemical vapor sensors. Three new transient feature models, enhanced exponential fitting, logarithmic linear fitting and piecewise linear fitting, have been proposed and optimized for precise discrimination against different chemical vapors. Compared with the conventional peak-to-peak method, these three new fitting algorithms significantly improved the prediction accuracy. Among them, the enhanced exponential fitting algorithm reaches the highest prediction accuracy of 92%, about 25% better than the conventional method. Although logarithmic and piecewise models exhibit slightly lower accuracy, they are much simpler and faster in computation than the exponential models. In the application of Internet of Things involving large number of sensors and sensor networks, a fast and accurate transient feature analysis is very important. This paper described a new route in achieving high-performance sensor technologies.

A Low Power and Low Complexity Automatic White Balance Algorithm for AMOLED Driving Using Histogram Matching

This paper presents a low power, low complexity and high hardware efficiency automatic white balance algorithm based on histogram matching (AWB-HM) for active-matrix organic light-emitting diode (AMOLED) driving. The main idea of AWB-HM algorithm is to reduce the display power by power constraint, and then increase the overlap area (OA) of three color histograms by histogram matching. The computation complexity in the proposed algorithm is reduced without estimating the gains of red, green, and blue channels in the conventional automatic white balance (AWB) algorithms. Moreover, adders rather than multipliers are mainly used in the algorithm, which is easier for the hardware realization. The simulation results show that the value of OA for the images processed by the proposed algorithm is 26.4% and 58.7% larger than that of gray-world (GW) and white-patch (WP) algorithm, respectively. Furthermore, the power dissipation and the time complexity is reduced compared with other algorithms. The proposed algorithm has been applied to AMOLED and the color cast of image is improved significantly.

A low spur CMOS phase-locked loop with wide tuning range for CMOS Image Sensor

A CMOS phase-locked loop (PLL) with low reference spur and wide tuning range implemented in 0.18μm CMOS technology is presented in this paper. The design is based on the programmable integer-N PLL structure and the center frequency is around 480MHz for CMOS Image Sensor applications. A pseudo-differential current-starved multi-band ring oscillator is proposed to widen the tuning range. Several circuit techniques are used to minimize the phase frequency detector (PFD) UP/DN timing mismatch and charge pump (CP) current glitches, which reduce the reference spur. Implemented in the 0.18μm CMOS technology, the simulation results show that the -52.6dBc reference spur and the 94.4% tuning range (covering from 30MHz to 1050MHz) can be achieved.

Characterization and optimization of the stacked–PN junction photodiodes structure for energy harvesting CMOS image sensor

The characterization and optimization of the stacked-PN junction photodiodes structure for energy harvesting CMOS image sensor is presented. The proposed structure has three desired PN junctions located along a vertical line. With proper connection, these PN junctions can provide high voltage or large current for the different load conditions. They also improve the energy harvesting efficiency compared with the conventional single PN junction. Theoretical analysis and optimizations of this structure are given in the paper as well as the simulation results.

A Vector-Quantization Compression Circuit With On-Chip Learning Ability for High-Speed Image Sensor

As the fundamental technology of autonomous vehicles and high-speed tracking, high-speed vision always suffers from the bottlenecks of on-chip bandwidth and storage due to the resource constraints. To improve the resource efficiency, we propose a hardware-efficient image compression circuit based on the vector quantization for a high-speed image sensor. In this circuit, a self-organizing map is implemented for the on-chip learning of codebook to flexibly satisfy the requirements of different applications. To reduce the hardware resources, we present a reconfigurable complete-binary-adder-tree, where the arithmetic units are reused completely. In addition, a mechanism of partial vector-component storage is adapted to make the compression ratio adjustable. Finally, a parallel-elementary-stream design ensures a high processing speed. The proposed circuit has been implemented on the field-programmable gate araray and also applied in a high-speed object tracking system. The experimental results indicate that it achieves an encoding speed of 722 frames/s with 128 weight vectors when working at 79.8 MHz, and the worst tracking error caused by the proposed circuit is merely 9 pixels. These results evince that our proposed circuit can be completely integrated with a high-speed image sensor and used in high-speed vision systems.

A small-area and low-power circuit implementation of color space conversion from RGB to YCbCr

This paper presents a small-area and low-power circuit implementation of high-precision color space conversion from RGB to YCbCr. Considering the particularity of image data, the paper put forward a novel and efficient common subexpression elimination (CSE) with image data segmentation. Consolidating every part of data appropriately according to the modified CSE algorithm, we will eventually get the transformed YCbCr within the acceptable mean square error (MSE). Besides, the synthesized results of a TSMC 0.18um standard cell library will be given. By using the proposed circuit implementation, the simulation results indicate that the area and power consumption could be 20% less than the conventional Canonic Signed Digital (CSD) method within almost the same accuracy

A pre-modulated step-up DC-DC converter with high-conductance switches

A pre-modulated step-up DC-DC converter with high-conductance switches is proposed in this paper. The modified switches used in the charge pump extend the gate-source voltage of PMOS power transistors and adjust the threshold voltage of NOMS ones based on body effect when the switches turn on, contributing to the increase of conductance. Pre-modulation technique works to maintain the output voltage to the expected level with the ripple smaller than 1mV. The proposed converter can achieve the peak efficiency of 87.2% while the output voltage ranges from 5V to 6.5V.

An area-efficient 10-bit two-stage DAC for active matrix organic light-emitting diodes display drivers

This paper presents a compact and area-efficient 10-bit DAC for active matrix organic light-emitting diodes (AMOLEDs) display drivers. The proposed DAC contains a voltage-selecting stage and a voltage-dividing stage. Compared with the conventional 10-bit capacitor-DAC, the switch number of decoders is reduced by 48.8%. A rail-to-rail class B buffer is utilized as the output buffer, which has a large transient driving capability with little static current. The simulation results show that the worst integral and differential nonlinearities are 1.16 LSB and 0.64 LSB, respectively, and the setting time within 0.1% error of the final voltage for a full swing is 6.43μs.

CMOS image sensor with programmable compressed sensing

The concept of compressed sensing CMOS image sensor is to compress data while sampling and prior to storage. This is our main idea to accomplish high speed imaging. In this paper, a CMOS image sensor with compressed sensing sampling mode is presented, which is composed of 256x256 pixel array. In order to reduce the complexity of the pseudo-random sequence generating circuits and reconstruction algorithm, the whole system is divided into 256 sub blocks. Each block consists of 16x16 pixel array with a single sigma-delta ADC, which is used to achieve the linear transformation. Similar to the conventional column ADC, the sigma-delta ADC is also used to quantize the transformed results. We have made a simulation for the proposed imaging architecture based on a 256x256 lena image. The simulation results show that the PSNR of the recovery image reaches 31.58 dB, 29.86 dB, and 29.52 dB, while the compressed ratio is 1/2, 1/4, and 1/6 respectively. Thus the corresponding frame rate can be increased by 2, 4, and 6 folds.