Songting Li

Reconfigurable All-Band RF CMOS Transceiver for GPS/GLONASS/Galileo/Beidou With Digitally Assisted Calibration

This paper presents a fully integrated reconfigurable all-band RF transceiver for GPS/GLONASS/ Galileo/Beidou in 55-nm CMOS. The transceiver incorporates three low-IF receivers (RXs) and one direct up-conversion BPSK transmitter (TX), which can be configured to receive any two global navigation satellite system (GNSS) signals or switched to process the Chinese Beidou(I) signals. A switching module is integrated to provide the connectivity between different RF front-end and IF channel (IFC), which will effectively simplify the design complexity of the IFC and save power consumption, while the GNSS signals are received. A flexible frequency plan with two frequency synthesizers is utilized to satisfy different local oscillator requirements of the transceiver. An optimized automatic frequency calibration scheme using an error compensation logic enables fast and high-precision calibration process for optimum phase-locked loop operation. Several digitally assisted calibration modules are integrated to ensure that the chip performance only shows a weak process, voltage and temperature (PVT) dependence. While drawing about 21.5-30.2 mA per RX channel from a 1.2-V supply, the RXs achieve an image rejection ratio more than 49 dB after I/Q mismatch calibration, an automatic gain control range of 88 dB, and an input-referred 1 dB compression point of better than -25 dBm with a minimum noise figure of about 2 dB. The output power of the TX is about 5 dBm with about 6% error vector magnitude (EVM) and 30-mA current from a 1.2-V supply. The whole transceiver consumes a die area of 2.8 × 3 mm2.

A Continuously and Widely Tunable 5 dB-NF 89.5 dB-Gain 85.5 dB-DR CMOS TV Receiver With Digitally-Assisted Calibration for Multi-Standard DBS Applications

This paper presents a direct-conversion, multi-standard TV receiver implemented in a 0.13 μm CMOS technology occupying less than 4 mm2. The receiver is compliant with several direct broadcasting satellite (DBS) standards, including DVB-S, DVB-S2, and ABS-S. A novel automatic frequency tuning (AFT) technique is adopted based on a searching algorithm to ensure less than 6% bandwidth deviation of the different bandwidths (over 40 bandwidth channels) for multi-standard applications. Moreover, digitally-assisted DC offset calibration is used to improve second-order distortion and calibration time of the receiver and the residual output offset achieved is less than 3 mV. An integrated ΣΔ fractional-N synthesizer utilizing an optimized automatic frequency calibration (AFC) scheme enables a fast and high-precision calibration process for dual-VCO phase-locked loop (PLL) operation. The measured linearity exceeds the desired target with the minimum margin in excess of 7 dBm, and the maximum carrier-to-noise ratio (CNR) values are better than 30 dB over wide input power levels, ensuring robust reception in variable environments. All circuit blocks are operated at 2.8 V stabilized by an LDO and consuming a total current of about 56 mA.

Reconfigurable All-band GNSS RF CMOS receiver

This paper presents a fully integrated reconfigurable all-band RF receiver for GPS/GLONASS/Galileo/Compass in 55 nm CMOS. The receiver incorporates two RF front-ends and two IF channels (IFC) to process any two GNSS signals. A switching module (SWM) is integrated to provide the connectivity between different RF front-end and IFC, which will effectively simplify the design complexity of the IFC and save power consumption. A flexible frequency planning with two frequency synthesizers is utilized to achieve the reception of any two GNSS signals. Several digitally-assisted calibration modules are integrated to ensure that the chip performance only shows a weak PVT dependence. While drawing about 26-29.2 mA per channel from a 1.2 V supply, this RF receiver achieve an image rejection ratio (IMRR) of more than 49 dB, an automatic gain control (AGC) range of 88 dB, and an input-referred 1 dB compression point (IP1dB) of better than -25 dBm with a noise figure (NF) of about 2 dB. The whole receiver consumes an active die area of about 3.5 mm2.

Multitime programmable (MTP) memory cell with pseudo differential architecture

A multitime programmable (MTP) memory cell based on pseudo differential architecture is presented in this paper. The proposed cell has only one floating gate, it takes advantage of the opposite polarity of PMOS transistor and NMOS transistor to output differential reading currents. The new cell has the same data retention capability as the state-of-the-art differential cell. Furthermore, it saves about 58% of the cell area with respect to the conventional differential cell. A test chip is fabricated by using a 0.13 μm standard CMOS process, and extensive experimental results are provided.

A LO generation system with optimized AFC scheme for multimode GNSS receivers

This paper presents a LO generation system used in multimode global navigation satellite system (GNSS) receivers in 55 nm CMOS. This system contains two PLL frequency synthesizers (FS) and supports simultaneous receiving of any two bands among GPS/GLONASS/Galileo/Compass systems with a flexible frequency plan. An optimized automatic frequency calibration (AFC) scheme using an error compensation logic enables fast and high-precision calibration process for optimum PLL operation. Measured results show that the phase noise of each FS is lower than -83 dBc/Hz and -110 dBc/Hz at 10 KHz and 1 MHz offset, respectively. And the locking time including AFC time and PLL time is only about 20 μs. The loop bandwidth varies by less than 6% for all GNSS signals and reference frequencies (10-80 MHz). Each FS consumes about 12 mA current from a 1.2 V supply, and the area of LO generation system is about 1.25 mm2.

A high linearity downconverter for digital broadcasting system

An integrated downconverter with high linearity for digital broadcasting system receivers is implemented in a 0.13 μm CMOS process with an active area of 0.1 mm2. The current-mode scheme is adopted to improve linearity performance by avoiding voltage fluctuation. A passive CMOS switching pair is utilized to improve the even-order linearity of the downconverter. A current amplifier is used to provide low input impedance which will easily lead to a wide operating bandwidth and high linearity. Moreover, a current-mode Sallen-Key low-pass filter is adopted for effective rejection of out-of-band interferers and also low input impedance. The digital-assisted DC offset calibration improves the second-order distortion of the downconverter. This design achieves a maximum gain of 40 dB and a dynamic range of 10 dB. Measured noise figure is 8.2 dB, an IIP2 of 63 dBm, an IIP3 of 17 dBm at the minimum gain of 30 dB. The downconverter consumes about 7.7 mA under a supply of 1.2 V.

Dual-band RF receiver for GPS-L1 and compass-B1 in a 55-nm CMOS

A fully integrated dual-band RF receiver with a low-IF architecture is designed and implemented for GPS-L1 and Compass-B1 in a 55-nm CMOS process. The receiver incorporates two independent IF channels with 2 or 4 MHz bandwidth to receive dual-band signals around 1.57 GHz respectively. By implementing a flexible frequency plan, the RF front-end and frequency synthesizer are shared for the dual-band operation to save power consumption and chip area, as well as avoiding LO crosstalk. A digital automatic gain control (AGC) loop is utilized to improve the receivers robustness by optimizing the conversion gain of the analog-to-digital converter (ADC). While drawing about 20 mA per channel from a 1.2 V supply, this RF receiver achieves a minimum noise figure (NF) of about 1.8 dB, an image rejection (IMR) of more than 35 dB, a maximum voltage gain of about 122 dB, a gain dynamic range of 82 dB, and an maximum input-referred 1 dB compression point of about −36.5 dBm with an active die area of 1.5 × 1.4 mm2 for the whole chip.

A fast and accurate automatic frequency calibration scheme for frequency synthesizer

A fully integrated 2.8-3.4 GHz frequency synthesizer that employs a novel automatic frequency calibration (AFC) is presented. The AFC is consists of a frequency error detector (FED) and a finite state machine (FSM). The error between VCO output frequency and the target frequency is calculated quickly and accurately due to the novel topology of PED which employs a utility phase detector (PD). Then a binary search algorithm is used by FSM to adjust capacitors code according to the frequency error. Finally the center frequency which is closest to the target frequency is found out as the optimal tuning curve. The total calibration cost only 0.611 μs. The frequency synthesizer is fabricated in 0.18-μm CMOS process and exhibits phase noise of -87.72 dBc/Hz at 10 KHz offset and -95.28 dBc/Hz at 100 kHz offset, while consuming 18 mW from a 1.8 V supply.

Dual-band RF receiver for GPS and compass systems in 55-nm CMOS

A fully integrated dual-band RF receiver with a low-IF architecture is designed and implemented for GPS-L1 and Compass-B1 in a 55-nm CMOS process. The receiver incorporates two independent IF channels with 2 or 4 MHz bandwidth to receive the dual-band signals around 1.57 GHz respectively. By implementing a flexible frequency plan, the RF front-end and frequency synthesizer are shared for the dual-band operation to save power consumption and chip area, as well as avoid any LO crosstalk. A digital automatic gain control (AGC) loop is utilized to improve the receivers robustness by optimizing the conversion gain of the analog-to-digital converter (ADC). While drawing about 20 mA per channel from a 1.2 V supply, this RF receiver achieves a minimum noise figure (NF) of about 1.8 dB, an image rejection (IMR) of more than 35 dB, a maximum voltage gain of about 110 dB, a gain dynamic range of more than 68 dB, and an input-referred 1 dB compression point (P1dB) of about -36.5 dBm with an active die area of 1.5 ×1.4 mm2 for the whole chip.

A Constant Loop Bandwidth Fraction-N Frequency Synthesizer for GNSS Receivers

A fully integrated 2.8 GHz to 3.4 GHz frequency synthesizer for satellite navigation RF resciever is implemented in 0.18-μm CMOS process and its area is 0.4 mm2. A constant and low tuning Gain (KVCO) is achieved by an improved voltage-controlled oscillator (VCO) architecture. The constant loop bandwidth, which is designed to 60 kHz, is implemented by making charge pump current (ICP) match the division ratio N. The synthesizer exhibits phase noise of -85.62 dBc/Hz at 10 KHz offset and -92.78 dBc/Hz at 100 kHz offset, while consuming 18 mW from a 1.8 V supply.