Zhaowen Zhuang

A Continuously and Widely Tunable 5 dB-NF 89.5 dB-Gain 85.5 dB-DR CMOS TV Receiver With Digitally-Assisted Calibration for Multi-Standard DBS Applications

This paper presents a direct-conversion, multi-standard TV receiver implemented in a 0.13 μm CMOS technology occupying less than 4 mm2. The receiver is compliant with several direct broadcasting satellite (DBS) standards, including DVB-S, DVB-S2, and ABS-S. A novel automatic frequency tuning (AFT) technique is adopted based on a searching algorithm to ensure less than 6% bandwidth deviation of the different bandwidths (over 40 bandwidth channels) for multi-standard applications. Moreover, digitally-assisted DC offset calibration is used to improve second-order distortion and calibration time of the receiver and the residual output offset achieved is less than 3 mV. An integrated ΣΔ fractional-N synthesizer utilizing an optimized automatic frequency calibration (AFC) scheme enables a fast and high-precision calibration process for dual-VCO phase-locked loop (PLL) operation. The measured linearity exceeds the desired target with the minimum margin in excess of 7 dBm, and the maximum carrier-to-noise ratio (CNR) values are better than 30 dB over wide input power levels, ensuring robust reception in variable environments. All circuit blocks are operated at 2.8 V stabilized by an LDO and consuming a total current of about 56 mA.

A LO generation system with optimized AFC scheme for multimode GNSS receivers

This paper presents a LO generation system used in multimode global navigation satellite system (GNSS) receivers in 55 nm CMOS. This system contains two PLL frequency synthesizers (FS) and supports simultaneous receiving of any two bands among GPS/GLONASS/Galileo/Compass systems with a flexible frequency plan. An optimized automatic frequency calibration (AFC) scheme using an error compensation logic enables fast and high-precision calibration process for optimum PLL operation. Measured results show that the phase noise of each FS is lower than -83 dBc/Hz and -110 dBc/Hz at 10 KHz and 1 MHz offset, respectively. And the locking time including AFC time and PLL time is only about 20 μs. The loop bandwidth varies by less than 6% for all GNSS signals and reference frequencies (10-80 MHz). Each FS consumes about 12 mA current from a 1.2 V supply, and the area of LO generation system is about 1.25 mm2.

A high linearity downconverter for digital broadcasting system

An integrated downconverter with high linearity for digital broadcasting system receivers is implemented in a 0.13 μm CMOS process with an active area of 0.1 mm2. The current-mode scheme is adopted to improve linearity performance by avoiding voltage fluctuation. A passive CMOS switching pair is utilized to improve the even-order linearity of the downconverter. A current amplifier is used to provide low input impedance which will easily lead to a wide operating bandwidth and high linearity. Moreover, a current-mode Sallen-Key low-pass filter is adopted for effective rejection of out-of-band interferers and also low input impedance. The digital-assisted DC offset calibration improves the second-order distortion of the downconverter. This design achieves a maximum gain of 40 dB and a dynamic range of 10 dB. Measured noise figure is 8.2 dB, an IIP2 of 63 dBm, an IIP3 of 17 dBm at the minimum gain of 30 dB. The downconverter consumes about 7.7 mA under a supply of 1.2 V.

Dual-band RF receiver for GPS-L1 and compass-B1 in a 55-nm CMOS

A fully integrated dual-band RF receiver with a low-IF architecture is designed and implemented for GPS-L1 and Compass-B1 in a 55-nm CMOS process. The receiver incorporates two independent IF channels with 2 or 4 MHz bandwidth to receive dual-band signals around 1.57 GHz respectively. By implementing a flexible frequency plan, the RF front-end and frequency synthesizer are shared for the dual-band operation to save power consumption and chip area, as well as avoiding LO crosstalk. A digital automatic gain control (AGC) loop is utilized to improve the receivers robustness by optimizing the conversion gain of the analog-to-digital converter (ADC). While drawing about 20 mA per channel from a 1.2 V supply, this RF receiver achieves a minimum noise figure (NF) of about 1.8 dB, an image rejection (IMR) of more than 35 dB, a maximum voltage gain of about 122 dB, a gain dynamic range of 82 dB, and an maximum input-referred 1 dB compression point of about −36.5 dBm with an active die area of 1.5 × 1.4 mm2 for the whole chip.

Dual-band RF receiver for GPS and compass systems in 55-nm CMOS

A fully integrated dual-band RF receiver with a low-IF architecture is designed and implemented for GPS-L1 and Compass-B1 in a 55-nm CMOS process. The receiver incorporates two independent IF channels with 2 or 4 MHz bandwidth to receive the dual-band signals around 1.57 GHz respectively. By implementing a flexible frequency plan, the RF front-end and frequency synthesizer are shared for the dual-band operation to save power consumption and chip area, as well as avoid any LO crosstalk. A digital automatic gain control (AGC) loop is utilized to improve the receivers robustness by optimizing the conversion gain of the analog-to-digital converter (ADC). While drawing about 20 mA per channel from a 1.2 V supply, this RF receiver achieves a minimum noise figure (NF) of about 1.8 dB, an image rejection (IMR) of more than 35 dB, a maximum voltage gain of about 110 dB, a gain dynamic range of more than 68 dB, and an input-referred 1 dB compression point (P1dB) of about -36.5 dBm with an active die area of 1.5 ×1.4 mm2 for the whole chip.

Noise and intermodulation mechanisms in CMOS downconverters

A noise and intermodulation distortion (IMD) analysis of CMOS downconverters, such as the widely used CMOS Gilbert cell, is presented. A qualitative physical model has been developed to explain the mechanisms responsible for noise and IMD in mixers. The contribution of all internal noise source and IMD to the output current is calculated through simple equations. The accuracy of the predictions about theory results are validated via comparing with simulation results, and the dependence of mixer noise and IMD on local oscillator (LO) amplitude and other circuit parameters are.

A 4–40MHz Active-RC chebyshev LPF with digital-assisted calibration for direct-conversion DVB-S/S2 & ABS-S TV tuners

A 4-40MHz fifth-order gain-adjustable LPF utilizing digital-assisted calibration for direct-conversion DVB-S/S2 & ABS-S TV tuners has been implemented in 0.13μm CMOS technology. The bandwidth of the filter can be changed from 4-16MHz with 0.5MHz step and 17-40MHz with 1MHz. The calibration includes automatic DC-offset Calibration (DCOC) and Automatic Frequency Tuning (AFT) to achieve less than 3mV residual output offset and 6% cut-off frequency deviation. The filter has -6-12dB gain range with 6dB step, less than 33.5nV/Hz1/2 input-referred noise, 30dBm IIP3, 59dBm IIP2, and draws 10.7mA from 2.8V supply.