Songwei Pei

An on-chip clock generation scheme for faster-than-at-speed delay testing

Faster-than-at-speed testing provides an effective way for detecting and debugging small delay defects in modern fabricated chips. However, the use of external automatic test equipment for faster-than-at-speed delay testing could be costly. In this paper, we present an on-chip clock generation scheme which facilitates faster-than-at-speed delay testing for both launch on capture and launch on shift test frameworks. The required test clock frequency with a high resolution can be obtained by specifying the information in the test patterns, which is then shifted into the delay control stages to configure the launch and capture clock generation circuit (LCCG) embedded on-chip. Similarly, the control information for selecting various test frameworks and clock signals can also be embedded in the test patterns. Experimental results are presented to validate the proposed scheme.

A Low Overhead On-Chip Path Delay Measurement Circuit

In this paper, we present a novel on-chip path delay measurement circuit for efficiently detecting and debugging of delay faults in the fabricated integrated circuits. Several delay stages are employed in the proposed circuit, whose delay ranges are increased by a factor of two gradually from the last to the first delay stage. Thus, the proposed method can achieve a large delay measurement range with a small quantity of delay stages. Experimental results show that a significant reduction in both delay measurement time and area overhead can be obtained compared to the previous Vernier Delay Line based delay measurement schemes. In addition, by conducting delay compensation, the proposed method can achieve both improved delay measurement resolution and measurement accuracy.

A High-Precision On-Chip Path Delay Measurement Architecture

In this paper, we present a novel on-chip path delay measurement architecture for efficiently detecting and debugging of delay faults in the fabricated integrated circuits. Several delay stages are employed in the proposed on-chip path delay measurement (OCDM) circuit, whose delay ranges are increased by a factor of two gradually from the last to the first delay stage. Thus, the proposed OCDM circuit can achieve a large delay measurement range with a small quantity of delay stages. A calibration circuit is incorporated into the proposed on-chip path delay measurement technique to calibrate the delay range of the delay stage under process variations. In addition, delay calibration for import lines is conducted to improve the precision of path delay measurement. Experimental results are presented to validate the proposed path delay measurement architecture.

Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume

We propose a flip-flop selection method to reduce the overall volume of transition delay test data, by replacing a small number of selected regular scan cells with enhanced scan cells. Relative measures are presented to reflect the gains when controlling a scan cell to a certain value, and guide the scan cell selection. Experimental results on larger IWLS 2005 benchmark circuits show that, to achieve the same fault coverage of the pure launch on capture (LOC) approach, the volume of test data can be reduced to a half on average by replacing only 1% of regular scan cells to enhanced scan cells. The transition delay fault coverage can also be improved using the proposed method with equally low area overhead.

Enhanced LCCG: A novel test clock generation scheme for faster-than-at-speed delay testing

On-chip faster-than-at-speed delay testing provides a promising way for small delay defect detection. However, the frequency of on-chip generated test clock would be impacted by process variations. Hence, it requires determining the actual frequency of generated test clock to ensure the effectiveness of faster-than-at-speed delay testing. In this paper, we present a novel test clock generation scheme, namely Enhanced LCCG, for faster-than-at-speed delay testing. In the proposed scheme, faster-than-at-speed test clock is firstly generated by configuring the corresponding control information specified in the test pattern into Enhanced LCCG. Then, by constructing oscillation paths and counting the corresponding oscillation iteration numbers, the actual frequency of test clock can be measured and calculated with high resolution. Experimental results are presented to validate the proposed method.

A unified architecture for speed-binning and circuit failure prediction and detection

With the continual scaling of semiconductor process technology, the circuit timing is increasingly impacted by process variations. It is thus important to categorize high-speed digital circuits into multiple bins of different performances. However, the speed-binning process typically needs very long test application time. In this paper, we proposed a unified architecture, which can accomplish performance grading with a high confidence and short test application time. Moreover, the proposed architecture can be used for on-line circuit failure prediction and detection. Experimental results are presented to validate the proposed architecture.

An on-chip frequency programmable test clock generation and application method for small delay defect detection

Small delay defects are posing a serious challenge to the quality and reliability of modern fabricated chips. A promising way for screening the timing-related defects in nanometer technology designs is faster-than-at-speed delay testing. However, the use of external automatic test equipment for faster-than-at-speed delay testing could be costly. In this paper, we present an on-chip frequency-programmable test clock generation method which facilitates faster-than-at-speed delay testing for both launch on capture and launch on shift test frameworks. With a reconfigurable launch-and-capture clock generator (LCCG) embedded on-chip, the required test clock, with a reconfigurable frequency and a high resolution, can be achieved by specifying the control information in the test patterns, which is then used to configure the LCCG. Similarly, the control information regarding test framework and clock signal selection can also be embedded in the test patterns. Experimental results are presented to validate the proposed method. A launch and capture clock generator (LCCG) is proposed for generating faster-than-at-speed test clock with programmable frequencies, which can be used to detect SDDs effectively by reducing the slacks of paths under test.The frequencies of faster-than-at-speed test clocks can be easily programmed by embedding the control information into the test patterns. Moreover, the frequencies of the generated test clocks have a high resolution and can achieve a large dynamic range.Both LOC and LOS test frameworks can be supported by the proposed method. The control information for selecting various test frameworks can also be embedded in the test patterns. The reason of not considering the ES test framework in this paper is that the enhanced scan delay testing approach is rarely used in industry for the unacceptable hardware overhead.With a programmable clock selection signal from the LCCG, a clock signal selector is designed to effectively support the application mode such as scan mode, functional operation mode, and test mode by selecting the required clock signal.Frequency variation of the generated test clock in the presence of process variations is analyzed. A method for preventing yield loss caused by frequency variation is presented, so that the test clock period can be programmed to leave a sufficient margin to avoid yield loss.The hardware overhead of the proposed LCCG and clock signal selector is very low, which isapproximately equal to that of 40 standard muxed-D scan cells and can be ignored by modern designs.

Variation-aware statistical energy optimization on voltage-frequency island based MPSoCs under performance yield constraints

Energy efficiency is a primary design concern for embedded multiprocessor system-on-chips (MPSoCs). Recently, Voltage-Frequency Island (VFI) - based design paradigm was introduced for fine-grained power management, which can seamlessly combine with the task scheduling algorithm to optimize system energy. However, the ever-increasing variabilities cause large uncertainty on delay and power. Such statistical nature in performance parameters easily makes deterministic energy optimization hard to achieve desirable performance yield, defined as the probability of the design meeting timing constraints of the system. In this paper, we propose a variation-aware statistical energy optimization framework, which takes account of performance yield constraints in energy-aware task scheduling, voltage assignment and VFI partitioning process. Energy optimization sensitivity, defined as energy variations of the task under voltage scaling, combines with the statistical slack of the task to guide the overall optimization flow. Experimental results demonstrate the effectiveness of the proposed scheme.

A unified test architecture for on-line and off-line delay fault detections

This paper proposes a unified delay test architecture, in which the design resources for on-line delay fault detection can be reused to support off-line delay testing. A stability checker, which has low hardware overhead, is presented to monitor the stability violation from each critical combinational output. A global error generator, which is shared among stability checkers, can produce a global error signal from individual stability checkers to indicate whether a delay fault appears. A local scan enable generator is incorporated into the scan chain to support scan-based off-line delay testing. Experimental results are presented to validate the effectiveness of the proposed approach.

Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan

Enhanced scan delay testing approach can achieve high transition delay fault coverage by a small size of test pattern set but with significant hardware overhead. Although the implementation cost of launch on capture (LOC) approach is relatively low, the generated pattern set for testing delay faults is typically very large. In this paper, we present a novel flip-flop selection method to combine the respective advantages of the two approaches, by replacing a small number of selected regular scan cells with enhanced scan cells, thus to reduce the overall volume of transition delay test patterns effectively. Moreover, higher fault coverage can also be obtained by this approach compared to the standard LOC approach. Experimental results on larger ISCAS-89 and ITC-99 benchmark circuits using a commercial test generation tool show that the volume of test patterns can be reduced by over 70% and the transition delay fault coverage can be improved by up to 8.7%.