Sorin Cotofana

A linear threshold gate implementation in single electron technology

In this paper we focus on the design of threshold logic functions in Single Electron Tunneling (SET) technology, using the tunnel junctions specific behavior i.e., the ability to control the transport of individual electrons. We introduce a novel design of an n-input linear threshold gate which can accommodate both positive and negative weights and built-in signal amplification, using 1 tunnel junction and n+2 true capacitors. As an example we present a 4-input threshold gate with both positive and negative weights.

A sum of absolute differences implementation in FPGA hardware

In this paper we propose a new hardware unit that performs a 16/spl times/1 SAD operation. The hardware unit is intended to augment a general-purpose core. Further we show that the 16/spl times/1 SAD implementation used can be easily extended to perform the 16/spl times/16 SAD operation, which is commonly used in many multimedia standards, including MPEG-1 and MPEG-2. We have chosen to implement the 16/spl times/1 SAD operation in field-programmable gate arrays (FPGA), because it provides increased flexibility, sufficient performance, and faster design times. We performed simulations to validate the functionality of the 16/spl times/1 SAD implementation using the MAX+plus 11 (version 9.23 BASELINE) software from Altera and synthesis using the FPGA Express (version 3.4) software from Synopsis. Targeting the Alteras FLEX20KE family, synthesis of our 16/spl times/1 SAD unit produced the following results for area and clock frequency: 1699 look-up tables (LUT) and 197 MHz, respectively.

Single electron encoded latches and flip-flops

Single electron tunneling (SET) technology offers the ability to control the transport of individual electrons. In this paper, we investigate single electron encoded logic (SEEL) memory circuits, in which the Boolean logic values are encoded as zero or one electron charges. More specifically, we focus on the implementation of SEEL latches and flip-flops. All proposed circuits are verified by means of simulation using the SIMulation Of Nanostructures package. We first present a generic SEEL linear threshold gate implementation, from which we derive a family of Boolean logic gates. Second, we propose Boolean gate-based implementations of the RS latch, the D latch, and D flip-flop. Third, we propose threshold gate-based implementations of the same memory elements. Finally, we discuss the estimated area, delay, and power consumption of the Boolean gate-based and threshold gate-based implementations, and compare them with other SET-based memory elements.

Addition related arithmetic operations via controlled transport of charge

This work investigates the single electron tunneling (SET) technology-based computation of basic addition related arithmetic functions, e.g., addition and multiplication, via a novel computation paradigm, which we refer to as electron counting arithmetic, that is based on controlling the transport of discrete quantities of electrons within the SET circuit. First, assuming that the number of controllable electrons within the system is unrestricted, we prove that the addition of two n-bit operands can be computed with a depth-2 network composed out of 3n+1 circuit elements and that the multiplication of two n-bit operands can be computed with a depth-3 network composed out of 4n-1 circuit elements. Second, assuming that the number of controllable electrons cannot be higher than a given constant r determined by practical limitations, we prove that the addition of two n-bit operands can be computed with a depth-(n/r+3) network composed out of 3n+1+n/r circuit elements. Under the same restriction, we suggest methods to reduce the addition network depth in the order of logn/r and to perform n-bit multiplication in an O(logn/r) delay. Finally, we propose SET-based implementations for a set of basic electron counting building blocks and implement a number of circuits operating under the electron counting paradigm as follows: 4-bit digital to analog converter, 5-bit analog to digital converter, 4-bit adder, and 3-bit multiplier. All proposed implementations are verified by means of simulation.

A unified aging model of NBTI and HCI degradation towards lifetime reliability management for nanoscale MOSFET circuits

As planar MOSFETs is approaching its physical scaling limitation, FinFET becomes one of the most promising alternative structure to keep on the industry scaling-down trend for future technology generations of 22 nm and beyond. In this paper, we propose a unified reliability model of Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) for double-gate and triple-gate FinFETs, towards a practical reliability assessment method for future FinFETs based circuits. The model is based on the reaction-diffusion theory and extends it such that it covers the FinFET specific geometrical structures. Apart of introducing the reliability model we also investigate the circuit performance degradation due to NBTI and HCI in order to create the premises for its utilization for assessing and monitoring the Integrated Circuits (ICs) aging process. To validate our model we simulated NBTI and HCI degradation and compared the obtained Vth shift prediction with the one evaluated based on experimental data. The simulations suggest that our model characterize the NBTI and HCI process with accuracy and it is computationally efficient, which makes it suitable for utilization in reliability-aware architectures as reliability prediction/assesment kernel for lifetime reliability management mechanisms.

2-1 addition and related arithmetic operations with threshold logic

In this paper we investigate the reduction of the size for small depth feed-forward linear threshold networks performing binary addition and related functions. For n bit operands we propose a depth-3 O(n/sup 2//log n) asymptotic size network for the binary addition with O polynomially bounded weights. We propose also a depth-3 addition of optimal O(n) asymptotic sits network and a depth-2 comparison of O(/spl radic/n) asymptotic size network, both with O(2/sup /spl radic/n/) asymptotic size of weight values. For existing architectural formats we show that our schemes, with equal or smaller depth networks, substantially outperform existing schemes in terms of size and fan-in requirements and on occasions in weight requirements.

Static buffered SET based logic gates

In this paper we investigate single electron tunneling (SET) devices from the logic design perspective, using the SET tunnel junctions ability to control the transport of individual electrons. In SET technology, small circuits containing only 1 tunnel junction (passive circuits) can form compact circuits implementing complex functions, but suffer from strong feedback effects. To alleviate this problem a dynamic buffer was proposed. However, this dynamic buffer has a behavior similar to a flip-flop and requires additional control signals. Therefore we first propose in this paper a static SET active buffer. The proposed static buffer switches output values by transporting one electron only and operates on a DC supply voltage. Second, we combine the proposed buffer with a threshold gate and derive static buffered NAND and NOR gates. We demonstrate our approach by presenting simulation results for a small network of gates, proving that the gates function correctly under a fanout of 4.

Field-Programmable Custom Computing Machines - A Taxonomy -

The ability for providing a hardware platformwhich can be customized on a per-application basis under software control has established Reconfigurable Computing (RC) as a new computing paradigm. A machine employing the RC paradigm is referred to as a Field-Programmable Custom Computing Machine (FCCM). So far, the FCCMs have been classified according to implementation criteria. For the previous classifications do not reveal the entire meaning of the RC paradigm, we propose to classify the FCCMs according to architectural criteria. To analyze the phenomena inside FCCMs, we introduce a formalism based on microcode, in which any custom operation performed by a field-programmed computing facility is executed as a microprogram with two basic stages: SET CONFIGURATION and EXECUTE CUSTOM OPERATION. Based on the SET/EXECUTE formalism, we then propose an architectural-based taxonomy of FCCMs.

Periodic symmetric functions, serial addition, and multiplication with neural networks

This paper investigates threshold based neural networks for periodic symmetric Boolean functions and some related operations. It is shown that any n-input variable periodic symmetric Boolean function can be implemented with a feedforward linear threshold-based neural network with size of O(log n) and depth also of O(log n), both measured in terms of neurons. The maximum weight and fan-in values are in the order of O(n). Under the same assumptions on weight and fan-in values, an asymptotic bound of O(log n) for both size and depth of the network is also derived for symmetric Boolean functions that can be decomposed into a constant number of periodic symmetric Boolean subfunctions. Based on this results neural networks for serial binary addition and multiplication of n-bit operands are also proposed. It is shown that the serial addition can be computed with polynomially bounded weights and a maximum fan-in in the order of O(log n) in O(n= log n) serial cycles, where a serial cycle comprises a neural gate and a latch. The implementation cost is in the order of O(log n), in terms of neural gates, and in the order of O(log2 n), in terms of latches. Finally, it is shown that the serial multiplication can be computed in O(n) serial cycles with O(log n) size neural gate network, and with O(n log n) latches. The maximum weight value in the network is in the order of O(n2) and the maximum fan-in is in the order of O(n log n).

An 8x8 IDCT Implementation on an FPGA-Augmented TriMedia

This paper presents an experiment which aims to assess the potential impact on performance yielded by augmenting a TriMedia/CPU64 processor with a reconfigurable core. We first propose the skeleton of an extension of the Tri-Media/CPU64 architecture, which consists of a Reconfigurable Functional Unit (RFU) and the associated instructions. Then, we address the computation of the 8×8 IDCT on such extended TriMedia and propose a scheme to implement the 1-D IDCT operation on the RFU. When implemented on an ACEX EP1K100 FPGA from Altera, the proposed 1-D IDCT exhibits a latency of 16 and a recovery of 2 TriMedia (200 MHz) cycles, and occupies 42% of the device. By configuring the 1-D IDCT computing facility on the RFU at application load-time, a 2-D IDCT including all overheads can be computed with the throughput of 1/32 IDCT/cycle. This is an improvement of more than 40% over the standard TriMedia/CPU64.