Sorin Cristoloveanu

A-RAM: Novel capacitor-less DRAM memory

A totally different capacitor-less, single-transistor memory cell (1T-DRAM) is proposed and documented. Its novelty comes from the body partitioning in two distinct regions, where electrons and holes are respectively confined. As compared to earlier 1T-DRAMs, the coexistence and coupling of electrons and holes is maintained even in ultrathin fully depleted MOSFETs. Selected simulations demonstrate attractive performance and great potential for embedded memory applications.

Evidence for mobility enhancement in double-gate silicon-on-insulator metal-oxide-semiconductor field-effect transistors

The methodology of mobility extraction from the Y-function or from the transconductance peak is revisited in the context of silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs). Based on a simple two-channel model, we discuss the biasing conditions that enable the Y-function to be applied to both single-gate (SG) and double-gate (DG) modes. Systematic mobility measurements in thick and ultrathin SOI transistors are presented for the front channel, back channel, and in quasi-double-gate mode. In SG-mode, the mobility is overestimated as soon as the opposite channel is activated. In partially depleted or relatively thick, fully depleted MOSFETs, the two channels are separated; hence, the total apparent mobility in DG mode is the sum of the front and back channel mobilities. By contrast, the two-channel model fails in ultrathin transistors, where the two channels become strongly coupled and volume inversion occurs. Volume inversion is reflected in a remarkable increase of t...

Challenges and Progress in Germanium-on-Insulator Materials and Device Development towards ULSI Integration

SOITEC, Parc Technologique des Fontaines, F38190, Bernin, France The recent progress in the fabrication of GeOI substrates and devices is reviewed. Improvements have been made in threading dislocation density, Ge-buried oxide interface passivation, device performance. The potential of various co-integration schemes (lateral and vertical) has been illustrated as alternatives to the fabrication of n-type germanium channel devices. GeOI is also shown to be a versatile platform for the monolithic integration of Si and III-V devices and tunneling field effect transistors.

Supercoupling effect in short-channel ultrathin fully depleted silicon-on-insulator transistors

Supercoupling effect prevents the simultaneous formation of inversion and accumulation channels at the two interfaces of ultrathin silicon-on-insulator metal-oxide-semiconductor field-effect transistor. Our work highlights that short-channel effects enhance supercoupling and turn it into a two-dimensional mechanism. The lateral influence of source and drain terminals is evidenced with experimental data and examined by 2D numerical simulations which reveal the roles of gate length and drain bias. The critical Si-film thickness, below which supercoupling arises, is significantly increased in short-channel transistors. The impact of back-gate and drain bias, BOX thickness, and quantum effects is documented and practical applications are discussed.

Bias-Engineered Mobility in Advanced FD-SOI MOSFETs

Ground-plane (GP) biasing in fully depleted silicon-on-insulator (FD-SOI) MOSFETs allows not only the tuning of the threshold voltage, but also the mobility improvement. We study the carrier mobility enhancement by introducing the return point (or minimum value) of the effective field. This parameter defines the optimum GP bias condition to maximize the mobility gain. Different regions of operation can be discriminated according to the monotonic increase or decrease of the effective field with the front-gate bias. For large mobility enhancement, the return point voltage Vret is adjusted via GP bias such as to exceed the threshold voltage. Experimental results show mobility gains over 70% in SOI MOSFETs with ultrathin buried oxide (10 nm) and Si film (8 nm).

A theoretical interpretation of magnetoresistance mobility in silicon inversion layers

The magnetoresistance technique has been introduced recently as a means of determining experimentally the mobility in bulk metal-oxide-semiconductor transistor and silicon-on-insulator devices. This technique does not require a precise determination of the channel length, and it also has the advantage of allowing mobility extraction when the application of other methods is problematic, notably with weak inversion and short device length. The magnetoresistance mobility extracted in this way is related but not identical to the normal effective drift mobility. In this work we simulate electron transport in the presence of a magnetic field for different device structures. The simulations allow us to study the conditions under which magnetoresistance mobility and effective mobility coincide, and to measure the difference, where it exists. We find that at low temperatures the two quantities coincide, while at room temperature a difference of more than 20% may appear. We take this to be a consequence of the ener...

Impact of back-gate biasing on effective field and mobility in ultrathin silicon-on-insulator metal-oxide-semiconductor field-effect-transistors

We discuss the role of back-gate biasing on effective field (Eeff) and its impact on the mobility in advanced ultrathin semiconductor-on-insulator metal-oxide-semiconductor field-effect-transistors using the multibranch mobility analysis. This technique is enabled using the integral definition for Eeff, which is the accurate method to determine Eeff even in volume-conduction regime. For further clarification, the difference between Eeff estimated by this integral definition and by the conventional formula is examined for our target devices. From the multibranch mobility analysis, we show that in devices with thin-buried oxide and ground plane doping, the reduction in Eeff due to back-gate biasing is large, leading to a significant mobility enhancement for both N-channel and P-channel devices. Furthermore, we show that the mobility enhancement effect via back-gate biasing in P-channel devices is larger than that in N-channel devices. This enhancement is attributed to the increase in the mobility under the ...

Properties of 22nm node extremely-thin-SOI MOSFETs

We have investigated the characteristics of 6nm thick, 22nm-node SOI MOSFETs by comparing the transport properties at the front (high-k) and back (SiO2) interfaces in a temperature range from −50° to 250°C. In addition to the mobility degradation with the channel length, an unusual mobility decrease at the SiO2 interface is observed in very narrow devices. For the shorter, narrower and thinner devices the transport characteristics tend to be the same regardless the interface where the carriers flow. Finally interface coupling dependence has been used to extract the density of states at the back interface.

Dual Ground Plane EDMOS in ultrathin FDSOI for 5V energy management applications

A promising high-voltage MOSFET (HVMOS) in Ultra-Thin Body and Buried oxide Fully Depleted SOI technology (UTBB-FDSOI) is experimentally demonstrated. The Dual Ground Plane Extended-Drain MOSFET (DGP EDMOS) architecture uses the back-gate biasing as an efficient lever to optimize high-voltage performances. We show that the separated biasing of the two ground planes enables independent control of the channel and drift regions. Electrical characteristics such as specific on-resistance/breakdown trade-off as a function of the back-gate voltage and geometry are explored. We present and discuss encouraging results for 5V switched mode applications for energy management.

Self-heating effects in ultrathin FD SOI transistors

We report the impact of self-heating effects (SHE) in 22nm-node Silicon on Insulator transistors with 6nm of silicon film thickness using a high-resolution current setup. The experiments show that, although the impact of SHE is less significant than in high-voltage devices, their role is still present. The average temperature increase in the channel due to self-heating is larger in the longer devices being responsible for decrease in the mobility and threshold voltage.