C. Fenouillet-Beranger

Plasma wave detection of terahertz radiation by silicon field effects transistors: Responsivity and noise equivalent power

Si metal oxide semiconductor field effect transistors (MOSFETs) with the gate lengths of 120–300nm have been studied as room temperature plasma wave detectors of 0.7THz electromagnetic radiation. In agreement with the plasma wave detection theory, the response was found to depend on the gate length and the gate bias. The obtained values of responsivity (⩽200V∕W) and noise equivalent power (⩾10−10W∕Hz0.5) demonstrate the potential of Si MOSFETs as sensitive detectors of terahertz radiation.

28nm FDSOI technology platform for high-speed low-voltage digital applications

For the first time, a full platform using FDSOI technology is presented. This work demonstrates 32% and 84% speed boost at 1.0V and 0.6V respectively, without adding process complexity compared to standard bulk technology. We show how memory access time can be significantly reduced thanks to high Iread, by keeping competitive leakage values. Yield of ~14Mb SRAM cells is demonstrated, allowing to measure for the first time Vmin of SRAM arrays.

High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding

Sources responsible for local and inter-die threshold voltage (V_t) variability in undoped ultra-thin FDSOI MOSFETs with a high-k/metal gate stack are experimentally discriminated for the first time. Charges in the gate dielectric and/or TiN gate workfunction fluctuations are determined as major contributors to the local V_t variability and it is found that SOI thickness (T_Si) variations have a negligible impact down to T_Si=7 nm. Moreover, T_Si scaling is shown to limit both local and inter-die V_t variability induced by gate length fluctuations. The highest matching performance ever reported for 25 nm gate length MOSFETs is achieved (A_Vt=0.95 mV.mum), demonstrating the effectiveness of the undoped ultra-thin FDSOI architecture in terms of V_t variability control.

Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond

We fabricated CMOS devices on Ultra-Thin Boby and Buried Oxide SOI wafers using a single mid-gap gate stack. Excellent global, local and intrinsic V<inf>T</inf>-variability performances are obtained (A<inf>VT</inf>=1.45mV.µm). This leads to 6T-SRAM cells with good characteristics down to V<inf>DD</inf>=0.5V supply voltage and with excellent Static Noise Margin (SNM) dispersion across the wafer (σ<inf>SNM</inf><SNM/6) down to V<inf>DD</inf>=0.7V. We also demonstrate ultra-low leakage (<0.5pA/µm) on UT2B devices at L<inf>G</inf>= 30nm by source/back biasing thanks to a low gate current and Gate Induced Drain Lowering (GIDL).

Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond

Recent device developments and achievements have demonstrated that planar undoped channel Fully depleted SOI devices are becoming a serious alternative to Bulk technologies for 20nm node and below. We have proven this planar option to be easier to integrate than the non planar devices like FinFET. This paper gives an overview of the main advantages provided by this technology, as well as the key challenges that need to be addressed. Electrostatic integrity, drivability, within wafer variability and scalability are addressed through silicon data (down to 18nm gate length) and TCAD analyses. Solutions to the Multiple VT challenges and non logic devices (ESD, I/Os) are also reported.

Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 μm 2 6T-SRAM bitcell

In this paper, we report on FD-SOI with high-k and single metal gate as a possible candidate for the 32 nm LOP and LSTP nodes. Good I_on/I_off performance for nMOS and pMOS transistors in the ultra-low-leakage regime (I_off=6.6 pA/μm) are presented. In addition co-integration of high voltage devices with EOT 29A/V_dd 1.8 V are made. For the first time, the functionality of 0.248 μm and 0.179 μm² 6T-SRAM bit-cells is demonstrated on FDSOI technology with a high-k/metal gate stack.

Efficient multi-V T FDSOI technology with UTBOX for low power circuit design

For the first time, Multi-V<inf>T</inf> UTBOX-FDSOI technology for low power applications is demonstrated. We highlight the effectiveness of back biasing for short devices in order to achieve I<inf>ON</inf> current improvement by 45% for LVT options at an I<inf>OFF</inf> current of 23nA/µm and a leakage reduction by 2 decades for the HVT one. In addition, fully functional 0.299um² bitcells with 290mV SNM at 1.1V and Vb=0V operation were obtained. We also demonstrate on ring oscillators and 0.299µm² SRAM bitcells the effectiveness (ΔV<inf>T</inf> versus V<inf>b</inf> ∼ 208mV/V) of the conventional bulk reverse and forward back biasing approaches to manage the circuit static power and the dynamic performances.

3DVLSI with CoolCube process: An alternative path to scaling

3D VLSI with a CoolCube™ integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm2. This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube™ technology leads to high performance top transistors with Thermal Budgets (TB) compatible with bottom MOSFET integrity. Key enablers are the dopant activation by Solid Phase Epitaxy (SPE) or nanosecond laser anneal, low temperature epitaxy, low k spacers and direct bonding. New data on the maximal TB bottom MOSFET can withstand (with high temperatures but short durations) offer new opportunities for top MOSFET process optimization.

On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells

In this paper, an in-depth variability analysis, i.e., from the threshold voltage V_T of metal-oxide-semiconductor field-effect-transistors (MOSFETs) to the static noise margin (SNM) of static random-access memory (SRAM) cells, is presented in fully depleted silicon-on-insulator (FDSOI) technology. The local V_T variability σ(V)_T lower than A(V)_T = 1.4 mV · μm is demonstrated. We investigated how this good V_T variability is reported on the SNM fluctuations σ_SNM at the SRAM circuit level. It is found experimentally that σ_SNM is correlated directly to the σ(V)_T of SRAM transistors without any impact of the mean SNM value. The contributions of the individual MOSFETs in the SRAM cells have been determined quantitatively by using a homemade Simulation Program with Integrated Circuit Emphasis compact model calibrated on our FDSOI electrical characteristics. The V_T variability in n-channel MOSFETs (nMOSFETs) is more critical than that in p-channel MOSFETs for SNM fluctuations, and σ(V)_T in drive nMOSFETs is the key parameter to control for minimizing σ_SNM.

Work-function engineering in gate first technology for multi-V T dual-gate FDSOI CMOS on UTBOX

For the first time, we demonstrate low-V<inf>T</inf> (V<inf>Tlin</inf> ±0.32V) nMOS and pMOS adjusted in a gate first FDSOI technology by work-function engineering of TiN/TaAlN metal gates. Especially, for low-V<inf>T</inf> pMOS, various Chemical-Vapor-Deposited TaAlN stacks with optimized Al concentration have been studied to finely tune the work-function above midgap while maintaining good reliability and mobility. Short channel performance of 500µA/µm I<inf>ON</inf> and 245µA/µm I<inf>EFF</inf> at 2nA/µm I<inf>OFF</inf> and V<inf>DD</inf>=0.9V is reported on pMOS with a TaAlN gate. In addition, it is found that the combination of these two metal gates with either n- or p-doped ground planes below the Ultra-Thin Buried Oxide (BOX) can offer 4 different V<inf>T</inf> from 0.32V to 0.6V for both nMOS and pMOS, demonstrating a real multiple-V<inf>T</inf> capability for FDSOI CMOS while keeping the channel undoped and the V<inf>T</inf> variability around A<inf>VT</inf>=1.3mV.µm.