Sotirios Papaioannou

Active plasmonics in WDM traffic switching applications

With metal stripes being intrinsic components of plasmonic waveguides, plasmonics provides a “naturally” energy-efficient platform for merging broadband optical links with intelligent electronic processing, instigating a great promise for low-power and small-footprint active functional circuitry. The first active Dielectric-Loaded Surface Plasmon Polariton (DLSPP) thermo-optic (TO) switches with successful performance in single-channel 10 Gb/s data traffic environments have led the inroad towards bringing low-power active plasmonics in practical traffic applications. In this article, we introduce active plasmonics into Wavelength Division Multiplexed (WDM) switching applications, using the smallest TO DLSPP-based Mach-Zehnder interferometric switch reported so far and showing its successful performance in 4×10 Gb/s low-power and fast switching operation. The demonstration of the WDM-enabling characteristics of active plasmonic circuits with an ultra-low power × response time product represents a crucial milestone in the development of active plasmonics towards real telecom and datacom applications, where low-energy and fast TO operation with small-size circuitry is targeted.

A 320 Gb/s-Throughput Capable 2

We demonstrate a 2 × 2 silicon-plasmonic router architecture with 320 Gb/s throughput capabilities for optical interconnect applications. The proposed router platform relies on a novel dual-ring Dielectric-Loaded Surface Plasmon Polariton (DLSPP) 2 × 2 switch heterointegrated on a Silicon-on-Insulator (SOI) photonic motherboard that is responsible for traffic multiplexing and header processing functionalities. We present experimental results of a Poly-methyl-methacrylate (PMMA)-loaded dual-resonator DLSPP waveguide structure that uses two racetrack resonators of 5.5 μm radius and 4 μ m-long straight sections and operates as a passive add/drop filtering element. We derive its frequency-domain transfer function, confirm its add/drop experimental spectral response, and proceed to a circuit-level model for dual-ring DLSPP designs supporting 2 × 2 thermo-optic switch operation. The validity of our circuit-level modeled 2 × 2 thermo-optic switch is verified by means of respective full vectorial three-dimensional Finite Element Method (3D-FEM) simulations. The router setup is completed by means of two 4 × 1 SOI multiplexing circuits, each one employing four cascaded second order micro-ring configurations with 100 GHz spaced resonances. Successful interconnection between the DLSPP switching matrix and the SOI circuitry is performed through a butt-coupling design that, as shown via 3D-FEM analysis, allows for small coupling losses of as low as 2.6 dB. The final router architecture is evaluated through a co-operative simulation environment, demonstrating successful 2 × 2 routing for two incoming 4-wavelength Non-Return-to-Zero (NRZ) optical packet streams with 40 Gb/s line-rates.

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A comprehensive theoretical analysis of end-fire coupling between dielectric-loaded surface plasmon polariton and rib/wire silicon-on-insulator (SOI) waveguides is presented. Simulations are based on the 3-D vector finite element method. The geometrical parameters of the interface are varied in order to identify the ones leading to optimum performance, i.e., maximum coupling efficiency. Fabrication tolerances about the optimum parameter values are also assessed. In addition, the effect of a longitudinal metallic stripe gap on coupling efficiency is quantified, since such gaps have been observed in fabricated structures. Finally, theoretical results are compared against insertion loss measurements, carried out for two distinct sets of samples comprising rib and wire SOI waveguides, respectively.

2 Silicon-Plasmonic Router Architecture for Optical Interconnects

We demonstrate experimental evidence of the data capture and the low-energy thermo-optic tuning credentials of dielectric-loaded plasmonic structures integrated on a silicon chip. We show 7-nm thermo-optical tuning of a plasmonic racetrack-resonator with less than 3.3 mW required electrical power and verify error-free 10-Gb/s transmission through a 60-μm-long dielectric-loaded plasmonic waveguide.

Interfacing Dielectric-Loaded Plasmonic and Silicon Photonic Waveguides: Theoretical Analysis and Experimental Demonstration

We present the first system-level demonstration of an active plasmonic device in 10-Gb/s data traffic conditions. An asymmetric silicon-plasmonic Mach-Zehnder interferometer with dielectric-loaded plasmonic waveguides serving as the electrically controlled arms, operates as thermo-optic On/Off gating element with 2.8- μ s response time and 10.8-mW power consumption.

Data Transmission and Thermo-Optic Tuning Performance of Dielectric-Loaded Plasmonic Structures Hetero-Integrated on a Silicon Chip

We demonstrate the first system-level evaluation of an active plasmonic device in 10Gb/s data traffic conditions. Thermo-optic ON/OFF modulation with 3μs response time and 10mW power consumption is presented using an asymmetric MZI silicon-plasmonic gate.

Active Plasmonics in True Data Traffic Applications: Thermo-Optic On/Off Gating Using a Silicon-Plasmonic Asymmetric Mach–Zehnder Interferometer

We report the first experimental performance evaluation of a 75-μm-long plasmonic multimode interference switch that is hetero-integrated on a silicon-on-insulator platform, operating with 10-Gb/s data signals. The switch exhibits a 2.9-μs response time and 44.5% modulation depth, while the extinction ratio between the ports alters from 5.4 to -1.5 dB for 35-mW electrical (switching) power. Error-free performance was achieved.

First demonstration of active plasmonic device in true data traffic conditions: ON/OFF thermo-optic modulation using a hybrid silicon-plasmonic asymmetric MZI

We present a 2 × 2 hybrid silicon-plasmonic thermooptic (TO) asymmetric Mach-Zehnder interferometric (MZI) switch having only 40-μm long active cyclomer-loaded plasmonic phase arms. It requires less than 12 mW of power and has 2/5-μs ON/OFF-times, respectively, a modulation depth higher than 90% and a 13.2-dB extinction ratio. Data traffic evaluation has been carried out using 10-Gb/s nonreturn-to-zero streams, yielding error-free operation at both switching states with power penalties ranging between 1 to 4.8 dB. The use of the cyclomer loading having a higher TO coefficient than polymethyl methacrylate has resulted to the smallest footprint among plasmonic MZI TO switches reported so far.

Demonstration of a Plasmonic MMI Switch in 10-Gb/s True Data Traffic Conditions

The rapid increase in processor throughput is currently exceeding the electronic memory speed progress, forming the well-known “Memory Wall” problem, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In that perspective, optical RAMs storing and retrieving information in the form of light with ps-scale memory access times seem to hold the potential for replacing small-size caches, offering at the same time a cache memory system being fully-compatible with optically interconnected CPU-memory architectures. In this article, we present our recent work spanning from WDM-enabled optical RAM bank architectures with optical all-passive row/column decoder modules to a complete 16GHz optical cache memory physical layer design for Chip Multiprocessor configurations and up to the Si-based integrated optical RAM cell architectures currently pursued within the FP7 RAMPLAS project.

Ultracompact and Low-Power Plasmonic MZI Switch Using Cyclomer Loading

In this letter, we present new architectural perspectives in optical static RAM configurations by exploiting the wavelength dimension in address domain. We present a 2 × 4 optical RAM row decoder (RD) that relies its operation on an all-passive wavelength-selective filtering matrix ( λ-matrix), receiving WDM-formatted address bits (Wordline) as input. The 2 × 4 RD is followed by an semiconductor optical amplifier Mach-Zehnder interferometer access gate and a column decoding unit to provide complete optical RAM row access. Proof-of-concept experimental verification of a 2 × 4 optical RAM RD is shown at 10 Gb/s, providing error-free operation with a peak power penalty lower than 0.2 dB.