Sotiris Bantas

CMOS active-LC bandpass filters with coupled-inductor Q-enhancement and center frequency tuning

A novel CMOS circuit for obtaining a bandpass response from a triple-coupled-inductor arrangement is presented, featuring Q-enhancement and center frequency tuning by means of vector-modulating a current flowing through one of the coupled inductors. A 0.35-/spl mu/m CMOS LC filter prototype employing the technique has been fabricated and exhibits a center frequency tuning range of 11% around 1 GHz and Q values up to 180. The input 1-dB compression point is -13 dBm with Q set to 20 and a power consumption of 12.2 mW. Additionally, an input impedance matching scheme around a spiral transformer is presented, which tracks the center frequency of the filter. The active-LC approach can be applied to higher order filter responses and find applications in tunable building blocks for agile RF front ends and multistandard radios.

Novel Si integrated inductor and transformer structures for RF IC design

Planar and 3D Si passive inductive structures are presented, with respect to their application in RF ICs. The modeling of the structures is realized by the use of a custom CAD tool, SISP. It Is shown how, for the first time, fast answers to complex questions can be obtained before fabrication, such as: inductance boost of up to 600% in three-layer spiral inductors compared to planar ones, with no cost in quality factor; optimization of the insertion and return losses of integrated transformers under area reduction schemes; modeling of practical integrated baluns; effect of physical separation on the crosstalk between inductors. The accuracy of modeling results is established through measurements in an array of fabricated structures.

Performance limits of planar and multi-layer integrated inductors

The performance of integrated inductors is quantified, with respect to geometrical parameters and silicon process characteristics. A custom EDA tool is employed for modeling and simulating an assortment of inductor topologies under various process schemes. The aim is to outline inductor performance limits, mainly in terms of inductance, quality factor and resonant frequency. Also, guidelines are provided for their optimal physical design and for process enhancements that may benefit their performance in RF ICs.

FULL-WAVE MODELING OF STRIPLINE STRUCTURES IN MULTILAYER DIELECTRICS

A novel computational method based on full-wave analysis of stripline planar structures with vertical interconnects in multilayer dielectric media is presented. The method is based on the electric-field integral-equation solved with the Method of Moments (MoM). The special characteristics of stripline structures facilitate the extensive use of semi-analytical techniques to analyze the multilayer structures, limiting significantly the use of purely numerical techniques. The accuracy of the proposed modeling method is examined thoroughly with extensive numerical tests and the results are compared with results generated by commercial simulators for simple stripline structures.

An inductance modeling flow seamlessly integrated in the RF IC design chain

A novel design flow is introduced based on an efficient inductance modeler, supporting RLCk extraction for spiral inductors, transformers and RF interconnect lines. The modeler operates on a set of EM-derived algorithms that can model complex cross-coupled devices on any silicon substrate rapidly and reliably. A design flow is set up in Cadence SKILL, integrating the inductance modeler with the layout editor and RCX extraction tools. Spiral inductor parametric cells are provided, that can be extracted with full connectivity in a single netlist along with other layout devices and parasitics. The resulting netlist includes mutual coupling (k) elements and is produced automatically without need for user intervention or back-annotation. Measured results on RF silicon circuitry showcase the accuracy and efficiency of the inductance modeling flow. The introduced flow can evolve into a platform for RF intellectual property (IP) evaluation and trade.

CMOS tunable bandpass RF filters utilizing coupled on-chip inductors

A novel scheme for tunable integrated CMOS bandpass RF filters using magnetically coupled on-chip inductors is proposed. A filter designed in a 0.6 /spl mu/m CMOS process exhibits a blocking dynamic range of over 70 dB, when tuned at a center frequency in the range of 900-1000 MHz and a filter Q of 25.

RF passive device modeling and characterization in 65nm CMOS technology

Rapid passive device modeling is discussed in this work based on test structures fabricated in a 65nm CMOS process with M1-M9 copper metal layers and one aluminum metal layer AP. Capacitance extraction for overlapping microstrips and shielded microstrip structures is investigated. Individual capacitances are modeled in terms of area and fringe components, either between microstrips or between microstrips and silicon substrate. Good correlation to silicon data is achieved for the fabricated test structures. The validity of the proposed model is also investigated for complex passive devices such as inductors and interdigitated capacitors. Device metrics for both types of passive devices are investigated and compared to measured silicon data. Good agreement is achieved in all cases proving the accuracy of the proposed modeling approach.

A fast full-wave modeling methodology for stripline structures with vertical interconnects in multi-layer dielectrics

A novel full-wave methodology for the modeling of stripline planar structures with vertical interconnects in multi-layer dielectric media is presented. The methodology is based on the electric-field integral-equation, discretized by employing the method of moments (MoM). The special characteristics of stripline structures facilitate extensive analytical solutions, eliminating the need for complex numerical techniques. The mathematical formulation and the algorithmic implementation of the method are also described. The validity of the theoretical results is examined by a comparison of calculated and measured results for simple stripline structures.

Architecture considerations and integrated-passives-based design for a dual-mode GPRS-WLAN SiGe RF transceiver

Seamlessly roaming user applications in converging GSM-WLAN environments are creating the need for highly integrated, dual-mode transceivers, amenable to single-die integration on silicon. Based on the direct conversion principle, an efficient system architecture that can be switched between both standards is proposed. It is shown that, for implementing the dual-mode radio, the design of wideband RF cells and switches is called for, which is nontrivial. Appropriate design techniques based on the extensive usage of on-chip passives are proposed to address the design of the dual-mode RF circuitry and render their performance on silicon as predictable as possible. The development of a SiGe BiCMOS GPRS-WLAN transceiver is showcased. Measurement results are provided at the cell level, for a 1.8-2.5 GHz 24 dB-gain LNA and an embedded +24 dBm WLAN PA.