Soumik Ghosh

Energy-balancing task allocation on wireless sensor networks for extending the lifetime

Extending the wireless sensor networks lifetime has been the aim of several research efforts. Distributed in-network processing arises as a viable solution to extend the networks lifetime. It avoids assigning heavy computations to a single node which might otherwise lead to its significant energy depletion. Task scheduling and allocation play a major role in the efficiency of the distribution. This work proposes EBSEL, an e̲nergy-b̲alancing task s̲cheduling and allocation heuristic whose main purpose is to e̲xtend the networks l̲ifetime, through energy balancing. Balancing the energy consumption among the nodes can help avoid the disintegration of the network where some nodes die unnecessarily, while others still have high energy reserve. EBSEL was extensively simulated on random task graphs and on a task graph of a real-world application. Compared to related work, EBSEL achieved more than 50% increase in lifetime and up to 5% energy savings per iteration.

A novel high write speed, low power, read-SNM-free 6T SRAM cell

In the nano-scaled technologies, increasing sub-threshold leakage, dynamic power and degrading SNM pose major hurdle for future generation circuits, especially in SRAM arrays. In this paper, a novel high write speed, low power, read-SNM-free 6T SRAM cell is presented. Simulation using 128 times 16 SRAM array in 90 nm CMOS technology shows that the cell can achieve 64% faster write operation than the conventional cell. Experimental results show that the write and read energy of the proposed cell are 76.8% and 53% lesser than the conventional cell respectively. Write precharge energy for the proposed cell is almost 81% less than that of conventional cell. During read operation, the proposed cell does not induce any noise at data nodes (dasiaQpsila & dasiaQbarpsila) which makes it a read-SNM-free design.

A multi-modal automatic image registration technique based on complex wavelets

Image registration is considered one of the most fundamental and crucial pre-processing tasks in digital imaging. This paper describes a fast multimodal automatic image registration algorithm that handles the alignment of IR and visible images. A multiresolution approach based on Dual Tree-complex wavelet transform is employed to speed up the process. At the coarsest level, an accurate registration estimate for higher levels is achieved, using edge detection and cross correlation. Mutual Information, on the other hand, is applied at higher levels as a matching criterion applied to the six orientation bands of the complex wavelet. The process is completely automatic, and was tested on several sets of synthetic and real data. Experimental results show that the proposed technique exhibits better accuracy than DWT-based algorithms for uni and multi-modal cases.

A low power CMOS UWB pulse generator

The paper presents a low power CMOS pulse generator design for impulse based UWB applications. The basic structure of the design involves a variable length rectangle pulse generator, a CMOS quasi-Gaussian pulse shaping filter and a small monopole antenna model. Simulation results show the pulse after the antenna is compliant with the FCCs spectrum mask for 0~960 MHz band and has a power consumption of 234 muW at the pulse repetition frequency of 100 MHz. The CMOS circuit used to create the pulse generator is simple and lends itself to a low-power, single-chip UWB transmitter solution

Design and implementaion of a 2D-DCT architecture using coefficient distributed arithmetic [implementaion read implementation]

The paper describes the design and implementation of an 8 /spl times/8 2D DCT chip for use in low-power applications. The design exploits a coefficient distributed arithmetic (CoDA) scheme as opposed to the prevalent data distributed arithmetic (DDA) schemes to achieve low power consumption. The architecture uses no ROMs and uses minimum number of additions by exploiting the redundancy in the adder arrays. The described architecture for the CoDA scheme is implemented on FPGA and has been fabricated on silicon. The fabricated chip computes 8 /spl times/8 2D DCT @ 50 MHz consuming around 137mW of power.

A hybrid adaptive scheme based on selective Gaussian modeling for real-time object detection

Object detection is receiving a growing attention with the emergence of surveillance systems. This paper presents a hybrid adaptive scheme based on selective Gaussian modeling for detecting objects in complex outdoor scenes with gradual illumination changes and dense, moving background objects like swinging tree branches. The proposed technique combines simple frame difference (FD), simple adaptive background subtraction (BS), and accurate Gaussian modeling to benefit from the high detection accuracy of Mixture of Gaussian solution (MoG) in outdoor scenes while reducing the computations required, thus, making it faster and more suitable for real time surveillance applications. Moreover, by applying selective component matching and updating and hysteresis thresholding, the probability of detecting a background pixel as foreground decreases leading to better detection accuracy than MoG as demonstrated in the quantitative and qualitative comparison.

A gradient-based hybrid image fusion scheme using object extraction

This paper presents a new hybrid image fusion scheme that combines features of pixel and region based fusion, to be integrated in a surveillance system. In such systems, objects can be extracted from the different set of images due to background availability, and transferred to the new composite image with no additional processing usually imposed by other fusion approaches. The background information is then fused in a multi-resolution pixel-based fashion using gradient-based rules to yield a more reliable feature selection. According to Piella and Petrovic quantitative evaluation metrics, the proposed scheme exhibits a superior performance compared to existing fusion algorithms.

Runtime energy consumption estimation for server workloads based on chaotic time-series approximation

This article proposes a runtime model that relates server energy consumption to its overall thermal envelope, using hardware performance counters and experimental measurements. While previous studies have attempted system-wide modeling of server power consumption through subsystem models, our approach is different in that it links system energy input to subsystem energy consumption based on a small set of tightly correlated parameters. The proposed model takes into account processor power, bus activities, and system ambient temperature for real-time prediction on the power consumption of long running jobs. Using the HyperTransport and QuickPath Link structures as case studies and through electrical measurements on example server subsystems, we develop a chaotic time-series approximation for runtime power consumption, arriving at the Chaotic Attractor Predictor (CAP). With polynomial time complexity, CAP exhibits high prediction accuracy, having the prediction errors within 1.6% (or 3.3%) for servers based on the HyperTransport bus (or the QuickPath Links), as verified by a set of common processor benchmarks. Our CAP is a superior predictive mechanism over existing linear auto-regressive methods, which require expensive and complex corrective steps to address the nonlinear and chaotic aspects of the underlying physical system.

A novel 8T SRAM cell with improved read-SNM

As the MOSFETs channel length is scaling down, SRAM stability becomes the major concern for future technology. The cell becomes more susceptible to both process induced variation in device geometry and threshold voltage variability due to dopant fluctuation in the channel region. In this paper, a novel highly stable 8T SRAM cell is proposed which eliminate any noise induction during read operation and keep the read SNM as high as 468 mV at VDD = 1.2 V in 120 nm technology. The cell also supports low power operation at cell VDD as low as 0.34 V.This new asymmetric cell structure is capable of using differential sense technique for high speed read operation.

On integrated CMOS-MEMS system-on-chip

The paper reviews the state-of-the-art in the field of CMOS-based microelectromechanical systems (MEMS). The different CMOS MEMS fabrication approaches, pre-CMOS, intermediate-CMOS, and post-CMOS, are summarized and examples are given.