Soumyajit Dey

Shruti: an embedded text-to-speech system for Indian languages

In India, the recent increase in the number of people with physical impairments has necessitated the need for low-cost, portable, augmentative and alternative communication devices. The authors describe a text-to-speech system for Indian languages, which accepts the text input in two Indian languages, Bengali and Hindi, and produces near-natural audio output. This text-to-speech system has been ported to two common handheld platforms, namely, iPaq from Compaq and Cassiopeia from Casio, both running on a Microsoft Pocket PC.

Embedded Support Vector Machine : Architectural Enhancements and Evaluation

In recent years, research and development in the field of machine learning and classification techniques have gained paramount importance. The future generation of intelligent embedded devices will obviously require such classifiers working on-line and performing classification tasks in a variety of fields ranging from data mining to recognition tasks in image and video. Among different such techniques, support vector machines (SVMs) have been found to deliver state of the art performance thus emerging as the clear winner. In this work, the support vector machine learning and classification tasks are evaluated on embedded processor architectures and subsequent architectural modifications are proposed for performance improvement of the same

A Tag Machine Based Performance Evaluation Method for Job-Shop Schedules

This paper proposes a methodology for performance evaluation of schedules for job-shops modeled using tag machines. The most general tag structure for capturing dependences is shown to be inadequate for the task. A new tag structure is proposed. Comparison of the method with existing ones reveals that the proposed method has no dependence on schedule length in terms of modeling efficiency and it shares the same order of complexity with existing approaches. The proposed method, however, is shown to bear promise of applicability to other models of computation and hence to heterogeneous system models having such constituent models.

Synthesis of sampling modes for adaptive control

Recent studies have shown that adaptively regulating the sampling rate results in significant reduction in the computational resources of embedded software based control. Selecting a uniform sampling rate for a control loop is robust, but pessimistic for sharing processors among multiple control loops. Fine-grained regulation of periodicity achieves better resource utilization, but is hard to implement online in a robust way. However, an offline control theoretic analysis of the system illustrates the benefits of proper period selection for different modes. Such analysis reveals the necessity to automatically derive a multi-mode scheduler and converge on suitable periods for each mode. This paper proposes a methodology to automatically generate such a scheduler for an embedded real-time control system leveraging its design attributes. The proposed method provides significant gains in computational efficiency without trading off the performance.

Adaptive sharing of sampling rates among software based controllers

Recent control theoretic studies have shown that the sharing of electronic control unit (ECU) bandwidth among multiple controllers can be adaptively regulated to achieve better control performance as opposed to static bandwidth allocation to each controller. Unfortunately the ideal controllers cannot always be implemented, since the computational platform does not admit unrestricted choice of sampling periods for the controllers. Therefore the controllers for each combination of the sampling rates must be pre-synthesized. This paper develops an algorithmic basis for identifying the optimal feasible combination of sampling rates at various modes of a system consisting of multiple controllers. The proposed approach is shown to yield controllers that are feasible and having comparable benefits as compared to the ideal controllers.

A Kleene Algebra of Tagged System Actors

The tagged signal model (TSM) is a formal framework for modeling heterogeneous embedded systems. In the present work, we provide a representation of tagged systems using the semantics of Kleene algebra. Such an algebraic representation facilitates the usage of standard off-the-shelf theorem provers for reasoning about such systems for both behavioral verification through equivalence checking and property verification.

Multirate Sampling for Power-Performance Tradeoff in Embedded Control

Recent research has emphasized the benefits of adaptively regulating the sampling rate of a plant as a function of its state of operation. In this letter, we study the problem in the context of the wide variety of low power embedded systems, where sampling rate has a direct relationship with power consumption. We propose a methodology for designing multirate controllers that switch between sampling rates depending on the disturbance levels while operating under a given energy budget. Our empirical studies indicate that better control performance can be achieved within the energy budget by adaptive regulation of the sampling rate, thereby demonstrating the efficacy of our proposal.

An Approach to Software Performance Evaluation on Customized Embedded Processors

Evaluation of software performance on a given customized embedded processor is an important step in the design space exploration of embedded system architectures. Such evaluations help system designers in taking early design decisions regarding the hardware architecture most suitable for the target application. Simulation based performance evaluations, although very accurate, can be prohibitively slower. In this paper, we present a novel hybrid approach consisting of an initial simulation run (one time) followed by analysis of intermediate level (IR) application code by an evaluation engine. Our results show that the evaluation engine can accurately (more than 95%) estimate the excecution cycles of application or application task on a given customized embedded processor while it is at least an order of magnitude faster in terms of time taken.

Architectural Optimizations for Text to Speech Synthesis in Embedded Systems

The increasing processing power of embedded devices have created the scope for certain applications that could previously be executed in desktop environments only, to migrate into handheld platforms. An important feature of the computing systems of modern times is their support for applications that interact with the user by synthesizing natural speech output. Such applications deliver state of the art performance in desktop environments. However, the real-time performance of such applications in handheld platforms with on-line incoming text streams have not been explored till date. In this work, the performance of a text to speech synthesis application is evaluated on embedded processor architectures and modifications in the underlying hardware platform are proposed for real time performance improvement of the concerned application.

Divergence Aware Automated Partitioning of OpenCL Workloads

Heterogeneous partitioning is a key step for efficient mapping and scheduling of data parallel applications on multi-core computing platforms involving both CPUs and GPUs. Over the last few years, several automated partitioning methodologies, both static as well as dynamic, have been proposed for this purpose. The present work provides an in-depth analysis of control flow divergence and its impact on the quality of such program partitions. We characterize the amount of divergence in a program as an important performance feature and train suitable Machine Learning (ML) based classifiers which statically decide the partitioning of an OpenCL workload for a heterogeneous platform involving a single CPU and a single GPU. Our approach reports improved partitioning results with respect to timing performance when compared with existing approaches for ML based static partitioning of data parallel workloads.