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Dive into the research topics where Sourabh Khandelwal is active.

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Featured researches published by Sourabh Khandelwal.


IEEE Transactions on Electron Devices | 2011

A Physics-Based Analytical Model for 2DEG Charge Density in AlGaN/GaN HEMT Devices

Sourabh Khandelwal; Nitin Goyal; Tor A. Fjeldly

In this brief, we present a physics-based analytical model for 2-D electron gas density <i>ns</i> in AlGaN/GaN high-electron mobility transistors. The proposed model accounts for the interdependence between Fermi level <i>Ef</i> and <i>ns</i>. The model is developed by considering the variation of <i>Ef</i>, the first subband <i>E</i><sub>0</sub>, the second subband <i>E</i><sub>1</sub>, and <i>ns</i> with applied gate voltage <i>Vg</i>. The proposed model is in very good agreement with numerical calculations.


IEEE Electron Device Letters | 2016

Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor

Asif Islam Khan; Korok Chatterjee; Juan Pablo Duarte; Zhongyuan Lu; Angada B. Sachid; Sourabh Khandelwal; R. Ramesh; Chenming Hu; Sayeef Salahuddin

We report subthreshold swings as low as 8.5 mV/decade over as high as eight orders of magnitude of drain current in short-channel negative capacitance FinFETs (NC-FinFETs) with gate length Lg = 100 nm. NC-FinFETs are constructed by connecting a high-quality epitaxial bismuth ferrite (BiFeO3) ferroelectric capacitor to the gate terminal of both n-type and p-type FinFETs. We show that a self-consistent simulation scheme based on Berkeley SPICE Insulated-Gate-FET Model:Common Multi Gate model and Landau-Devonshire formalism could quantitatively match the experimental NC-FinFET transfer characteristics. This also allows a general procedure to extract the effective S-shaped ferroelectric charge-voltage characteristics that provides important insights into the device operation.


IEEE Transactions on Electron Devices | 2012

BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

Sourabh Khandelwal; Yogesh Singh Chauhan; Darsen D. Lu; Sriramkumar Venugopalan; Muhammed Ahosan Ul Karim; Angada B. Sachid; Bich Yen Nguyen; Olivier Rozeau; O. Faynot; Ali M. Niknejad; C. Hu

In this paper, we present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control. This work advances previous works in terms of numerical accuracy, computational efficiency, and behavior of the higher order derivatives of the drain current. We propose a consistent analytical solution for the calculation of front- and back-gate surface potentials and inversion charge. The accuracy of our surface potential calculation is on the order of nanovolts. The drain current model includes velocity saturation, channel-length modulation, mobility degradation, quantum confinement effect, drain-induced barrier lowering, and self-heating effect. The model has correct behavior for derivatives of the drain current and shows an excellent agreement with experimental data for long- and short-channel devices with 8-nm-thin silicon body and 10-nm-thin BOX.


IEEE Transactions on Electron Devices | 2012

Analytical Modeling of Surface-Potential and Intrinsic Charges in AlGaN/GaN HEMT Devices

Sourabh Khandelwal; Yogesh Singh Chauhan; Tor A. Fjeldly

A surface potential (SP)-based analytical model for intrinsic charges in AlGaN/GaN high electron mobility transistor devices is presented. We have developed a precise analytical method to calculate the Fermi-level position Ef from a consistent solution of Schrodingers and Poissons equations in the quantum well, considering the two important energy levels. The accuracy of our Ef calculation is on the order of femto-volts for the full range of bias voltage. The SP calculated from Ef is used to derive an analytical model for intrinsic charges in these devices. The model is in excellent agreement with experimental data.


IEEE Transactions on Electron Devices | 2014

BSIM6: Analog and RF Compact Model for Bulk MOSFET

Yogesh Singh Chauhan; Sriramkumar Venugopalan; Maria-Anna Chalkiadaki; Muhammed Ahosan Ul Karim; Harshit Agarwal; Sourabh Khandelwal; Juan Pablo Duarte; Christian Enz; Ali M. Niknejad; Chenming Hu

BSIM6 is the latest industry-standard bulk MOSFET model from the BSIM group developed specially for accurate analog and RF circuit designs. The popular real-device effects have been brought from BSIM4. The model shows excellent source-drain symmetry during both dc and small signal analysis, thus giving excellent results during analog and RF circuit simulations, e.g., harmonic balance simulation. The model is fully scalable with geometry, biases, and temperature. The model has a physical charge-based capacitance model including polydepletion and quantum-mechanical effect thereby giving accurate results in small signal and transient simulations. The BSIM6 model has been extensively validated with industry data from 40-nm technology node.


IEEE Transactions on Electron Devices | 2013

Robust Surface-Potential-Based Compact Model for GaN HEMT IC Design

Sourabh Khandelwal; Chandan Yadav; Shantanu Agnihotri; Yogesh Singh Chauhan; Arnaud Curutchet; Thomas Zimmer; Jean-Claude De Jaeger; Nicolas Defrance; Tor A. Fjeldly

We present an accurate and robust surface-potential-based compact model for simulation of circuits designed with GaN-based high-electron mobility transistors (GaN HEMTs). An accurate analytical surface-potential calculation, which we developed, is used to develop the drain and gate current model. The model is in excellent agreement with experimental data for both drain and gate current in all regions of device operation. We show the correct physical behavior and mathematical robustness of the model by performing various benchmark tests, such as DC and AC symmetry tests, reciprocity test, and harmonic balance simulations test. To the best of our knowledge, this is the first time a GaN HEMT compact model passing a range of benchmark tests has been presented.


IEEE Transactions on Electron Devices | 2013

Compact Charge-Based Physical Models for Current and Capacitances in AlGaN/GaN HEMTs

F. M. Yigletu; Sourabh Khandelwal; Tor A. Fjeldly; Benjamin Iniguez

This paper presents physics-based compact models for the C-V and I-V characteristics of AlGaN/GaN HEMT devices. The contribution of only the first energy level in the triangular quantum well at the AlGaN/GaN interface (where most of the charge carriers of the 2-DEG channel reside) is considered, which resulted in an accurate and simple unified charge control model. Based on this, analytical models of the drain current, the gate charge, and the gate capacitances have been developed. The models cover all the different operating regimes of a device. The excellent agreements between the model and measured C-V and I-V characteristics of devices with different gate lengths have demonstrated the validity of the model.


IEEE Transactions on Electron Devices | 2015

Surface-Potential-Based Compact Modeling of Gate Current in AlGaN/GaN HEMTs

Sudip Ghosh; Avirup Dasgupta; Sourabh Khandelwal; Shantanu Agnihotri; Yogesh Singh Chauhan

In this paper, the gate current in AlGaN/GaN high-electron mobility transistors is modeled analytically in a surface potential-based compact model. Thermionic emission and Poole-Frenkel emission are two dominant mechanisms for the gate current in the forward and reverse-bias regions, respectively. In addition, a trap-assisted tunneling component, which is important at low reverse bias, is also added. The developed gate current model, implemented in Verilog-A is in excellent agreement with experimental data and passes the important Gummel symmetry test.


IEEE Transactions on Electron Devices | 2016

Capacitance Modeling in Dual Field-Plate Power GaN HEMT for Accurate Switching Behavior

Sheikh Aamir Ahsan; Sudip Ghosh; Khushboo Sharma; Avirup Dasgupta; Sourabh Khandelwal; Yogesh Singh Chauhan

In this paper, a surface-potential-based compact model is proposed for the capacitance of an AlGaN/GaN high-electron mobility transistor (HEMT) dual field-plate (FP) structure, i.e., with gate and source FPs. FP incorporation in a HEMT gives an improvement in terms of enhanced breakdown voltage, reduced gate leakage, and so on, but it affects the capacitive nature of the device, particularly by bringing into existence in a subthreshold region of operation, a feedback miller capacitance between the gate and the drain, and also a capacitance between the drain and the source, therefore, affecting switching characteristics. Here, we model the bias dependence of the terminal capacitances, wherein the expressions developed for intrinsic charges required for capacitance derivation are analytical and physics-based in nature and valid for all regions of device operation. The proposed model, implemented in Verilog-A, is in excellent agreement with the measured data for different temperatures.


IEEE Transactions on Electron Devices | 2016

Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part I: Model Description

Girish Pahwa; Tapas Dutta; Amit Agarwal; Sourabh Khandelwal; Sayeef Salahuddin; Chenming Hu; Yogesh Singh Chauhan

We present an accurate and computationally efficient physics-based compact model to quantitatively analyze negative capacitance FET (NCFET) for real circuit design applications. Our model is based on the Landau-Khalatnikov equation coupled to the standard BSIM6 MOSFET model and implemented in Verilog-A. It includes transient and temperature effects, and accurately captures different aspects of NCFET. A comprehensive quasi-static analysis of NCFET in its different regions of operation is also performed using a simpler loadline approach. We also analyze the impact of ferroelectric and gate oxide thicknesses on the performance gain of NCFET over MOSFET.

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Yogesh Singh Chauhan

Indian Institute of Technology Kanpur

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Chenming Hu

University of California

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Tor A. Fjeldly

Norwegian University of Science and Technology

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Sudip Ghosh

Indian Institute of Technology Kanpur

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Sheikh Aamir Ahsan

Indian Institute of Technology Kanpur

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Avirup Dasgupta

Indian Institute of Technology Kanpur

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