Pragya Kushwaha

Recent enhancements in BSIM6 bulk MOSFET model

In this paper, we discuss the recent enhancements made in the BSIM6 bulk MOSFET model. BSIM6 is the latest compact model of bulk MOSFET from BSIM group which have body referenced charge based core. Junction capacitance model is improved over BSIM4 and is infinitely continuous around Vbs=Vbd=0V. Symmetry of the model is successfully validated by performing Gummel Symmetry Test (GST) in DC and symmetry test for capacitances in AC. Self heating model is also included in BSIM6 and test results are reported. Model capabilities are compared against an advanced 40nm CMOS technology and it is observed that simulated results are in excellent agreement with the measured data.

Modeling of GaN-Based Normally-Off FinFET

In this letter, a macromodel for normally-off (enhancement mode) AlGaN/GaN-based FinFET (2-DEG channel at top with two MOS like sidewall channels) is proposed. AlGaN/GaN-based FinFET devices have improved gate control on the channel due to additional sidewall gates compared with planar structures, but device characteristics exhibit strong nonlinear dependence on fin-width. The proposed model captures both 2-DEG and sidewall channel conduction as well as the fin-width dependency on device characteristics. Model shows excellent agreement with state-of-the-art experimental data.

RF Modeling of FDSOI Transistors Using Industry Standard BSIM-IMG Model

In this paper, RF modeling and step-by-step parameter extraction methodology of the BSIM-IMG model are discussed with experimental data. BSIM-IMG is the latest industry standard surface potential based model for fully depleted silicon-on-insulator (FDSOI) transistors. The impact of gate, substrate, and thermal networks is demonstrated with S-parameter data, which enable the BSIM-IMG model to capture RF behavior of the FDSOI transistor. The model is validated over a wide range of biases and frequencies and excellent agreement with the experimental data is obtained.

Unified Compact Model Covering Drift-Diffusion to Ballistic Carrier Transport

In this letter, we present a unified compact model, which accurately captures carrier transport from the drift-diffusion to ballistic regime. This is a single unified model, which accounts for carrier degeneracy effects in ballistic transport. The model is implemented into the industry standard compact models for FinFETs, fully depleted silicon-on-insulator (FDSOI) devices and bulk MOSFETs: 1) Berkeley Spice model for common multi-gate; 2) Berkeley Spice model for independent multi-gate; and 3) BSIM6. The model is validated with experimental data and TCAD simulations for FDSOI devices, FinFETs, and bulk MOSFETs.

Analytical Modeling and Experimental Validation of Threshold Voltage in BSIM6 MOSFET Model

In this paper, an analytical model of threshold voltage for bulk MOSFET is developed. The model is derived from the physical charge-based core of BSIM6 MOSFET model, taking into account short channel effects, and is intended to be used in commercial SPICE simulators for operating point information. The model is validated with measurement data from IBM 90-nm technology node using various popular threshold voltage extraction techniques, and good agreement is obtained.

BSIM-IMG: Compact model for RF-SOI MOSFETs

Emerging market of RFSOI applications has motivated us to come up with the robust compact model for RFSOI MOSFETs. In this work, we have validated the RF capabilities of BSIM-IMG model which is the latest industry standard compact model for independent double gate MOSFETs. Results are validated with the experimental S-parameter data measured. Model shows good agreement for different biases over wide frequency range from 100KHz-8.5GHz.

BSIM-CMG: Standard FinFET compact model for advanced circuit design

This work presents new compact models that capture advanced physical effects presented in industry FinFETs. The presented models are introduced into the industry standard compact model BSIM-CMG. The core model is updated with a new unified FinFET model, which calculates charges and currents of transistors with complex fin cross-sections. In addition, threshold voltage modulation from bulk-bias effects and bias dependent quantum mechanical confinement effects are incorporated into the new core model. Short channel effects, affecting threshold voltage and subhtreshold swing, are modeled with a new unified field penetration length, enabling accurate 14nm node FinFET modeling. The new proposed models further assure the BSIM-CMG models capabilities for circuit design using FinFET transistors for advanced technology nodes.

Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG

The channel in Fully Depleted Silicon On Insulator (FDSOI) transistors is completely isolated from the substrate via buried oxide (BOX) and from the sides by shallow trench isolations, which results in high thermal resistance (Rth). Further, Rth increases with reduction in channel length (Lg). In this paper, we have proposed a compact model for the geometry and temperature dependence of Rth in FDSOI transistors. The model is validated against experimental and Technology Computer Aided Design (TCAD) data. The proposed model is implemented in the independent multi-gate model (BSIM-IMG) for FDSOI transistors. Graphical abstractThe channel in Fully Depleted Silicon On Insulator (FDSOI) transistors is completely isolated from the substrate via buried oxide (BOX) and from the sides by shallow trench isolations, which results in high thermal resistance (Rth). Further, Rth increases with reduction in channel length (Lg). In this paper, we have proposed a compact model for the geometry and temperature dependence of Rth in FDSOI transistors. The model is validated against experimental and Technology Computer Aided Design (TCAD) data. We also validate the radio-frequency (RF) model with measured high frequency data. The proposed model is implemented in the independent multigate model (BSIM-IMG) for FDSOI transistors.Display Omitted HighlightsGeometrical scaling of thermal resistance in FDSOI transistor has been analyzed.A new behavioral model for thermal resistance scaling has been proposed.The model is validated against experimental and Technology Computer Aided Design (TCAD) data.The BSIM-IMG model is validated on the measured RF characteristics for wide bias and frequency ranges.

Characterization of RF Noise in UTBB FD-SOI MOSFET

In this paper, we report the noise measurements in the RF frequency range for ultrathin body and thin buried oxide fully depleted silicon on insulator (FD-SOI) transistors. We analyze the impact of back and front gate biases on the various noise parameters; along with discussions on the secondary effects in FD-SOI transistors which contribute to the thermal noise. Using calibrated TCAD simulations, we show that the noise figure changes with the substrate doping and buried oxide thickness.

BSIM-IMG with improved surface potential calculation recipe

In this paper, we have reported the improved surface potential calculation in the BSIM-IMG model for FDSOI MOSFETs. Model validation is done with the experimental data provided by Low-power Electronics Association and Project (LEAP). The model shows accurate behavior for C-V and I-V characteristics while keeping smooth behavior for their higher order derivatives. Model has smooth transition from weak inversion to strong inversion and satisfies DC and AC symmetry tests.