Spyros Kavadias

A logarithmic response CMOS image sensor with on-chip calibration

CMOS image sensors with logarithmic response are attractive devices for applications where a high dynamic range is required. Their strong point is the high dynamic range. Their weak point is the sensitivity to pixel parameter variations introduced during fabrication. This gives rise to a considerable fixed pattern noise (FPN) that deteriorates the image quality unless pixel calibration is used. In the present work a technique to remove the FPN by employing on-chip calibration is introduced, where the effect of threshold voltage variations in pixels is cancelled. An image sensor based on an active pixel structure with five transistors has been designed, fabricated, and tested. The sensor consists of 525/spl times/525 pixels measuring 7.5 /spl mu/m/spl times/10 /spl mu/m, and is fabricated in a 0.5-/spl mu/m CMOS process. The measured dynamic range is 120 dB while the FPN is 2.5% of the output signal range.

A single-chip digitally calibrated 5.15-5.825-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a wireless LAN

The drive for cost reduction has led to the use of CMOS technology in the implementation of highly integrated radios. This paper presents a single-chip 5-GHz fully integrated direct conversion transceiver for IEEE 802.11a WLAN systems, manufactured in 0.18-/spl mu/m CMOS. The IC features an innovative system architecture which takes advantage of the computing resources of the digital companion chip in order to eliminate I/Q mismatch and achieve accurately matched baseband filters. The integrated voltage-controlled oscillator and synthesizer achieve an integrated phase noise of less than 0.8/spl deg/ rms. The receiver has an overall noise figure of 5.2 dB and achieves sensitivity of -75 dBm at 54-Mb/s operation, both referred to the IC input. The transmit error vector magnitude is -33 dB at -5-dBm output power from the integrated power-amplifier driver amplifier. The transceiver occupies an area of 18.5 mm/sup 2/.

A 65 nm CMOS Multistandard, Multiband TV Tuner for Mobile and Multimedia Applications

This paper presents a direct conversion, multistandard TV tuner implemented on a 65 nm digital CMOS process occupying less than 7 . The tuner is compliant with several digital terrestrial, fixed and mobile TV standards, including DVB-T, DVB-H, T-DMB, and ISDB-T. It achieves a 3/3.2/3.5 dB noise figure at VHF, UHF, and L-band, respectively, while the measured sensitivity at UHF for the QPSK-frac12 DVB-T mode is at the PCB connector. The implemented RF front-ends support both single-ended and differential inputs. An integrated - fractional-N synthesizer operating from 1.2 to 1.8 GHz achieves less than 1 integrated phase error, thus enabling a maximum SNR in excess of 37 dB for VHF and UHF. Multistandard capability is also enabled by programmable channel-select filters. Power consumption is less than 140 mW in DVB-T mode for all three bands.

Calculation of pixel detector capacitances through three dimensional numerical solution of the Laplace equation

A method for the solution of the three dimensional Laplace equation is presented. The method applies to planar geometry cases, such as pixel detector devices, characterized by mixed boundary conditions. Through this algorithm the capacitances associated with pixel detectors are calculated. These capacitances, which are the pixel to substrate and the interpixel capacitances, are of great importance in the design of a pixel detector since they influence the noise and the cross talk effects between pixels. Capacitances for various pixel and interpixel dimensions are presented along with an analytical approximation for the calculation of the total pixel capacitance. >

The LEDA512 integrated circuit anode array for the analog recording of mass spectra

This article describes two generations of a novel integrated circuit multi-anode electron detector chip (LEDA512). This chip is designed for usage as an analog ion detector in magnetic mass spectrometers, in combination with a stack of two micro channel plates. The first generation chip is applied in a positive ion mass spectrometer on-board the ESA ROSETTA cometary mission. The detector chip comprises two identical and redundant parts, each consisting in a row of 512 rectangular anodes for electron collection, and in an anode multiplexer followed by a charge amplifier. A second-generation of the chip is scheduled. It will implement additional features, such as: radiation hard MOS transistors and shift registers and improved output drive capabilities.

A silicon pixel detector with integrated amplification devices

Abstract A new pixel detector with amplification at pixel level is proposed. This detector is based on lightly doped pixels that serve not only as the cathode electrodes but also as wells for the fabrication of field effect transistors. A noise analysis is presented leading to the optimum amplifier design and revealing an excellent noise performance.

A cost-efficient 0.18 /spl mu/m CMOS RF transceiver using a fractional-N synthesizer for 802.11b/g wireless LAN applications

A single-chip 2.4 GHz, zero-IF transceiver for IEEE 802.11 b/g WLAN systems is fabricated on a 0.18 /spl mu/m CMOS technology. Based on an innovative system architecture using digital calibration, analog circuit imperfections are eliminated. The transceiver features enhanced phase noise performance with the use of a fractional-N synthesizer. A switched configuration allows for the same filters to be used on both TX/RX paths, thus minimizing area. It features a NF of 3.5 dB while the sensitivity is -78 dBm at 54 Mb/s operation, referred at the input of the chip. The transmit output 1 dB compression point is 9 dBm. Digital calibration helps achieve an EVM of -31 dB while transmitting -4 dBm at 54 Mb/s.

A silicon drift detector with a P-type JFET integrated in the N-well anode

Abstract The work deals with calculations for and experimental results measured on a silicon drift detector having a p-type JFET integrated in its anode. A new device design and processing steps are presented based on the self-alignment of the transistor gate to the source and drain regions. The gate is formed by drive-in of phosphorus atoms from the deposited, implanted and patterned polysilicon overlayer. The accurate matching of the anode geometrical capacitance, as calculated from computer models, to the transistor capacitance is another feature of the our detector. Such improvements made possible a measured total anode capacitance of 140xa0fF and at the same time a transistor transconductance of 0.22xa0mS at room temperature.

A complementary metal–oxide–semiconductor anode array chip with two rows of 512 anodes and dual integrated analog read-out circuitry

A novel multianode electron detector chip (LEDA512) has been designed, fabricated and tested using a 0.7 μm complementary metal–oxide–semiconductor technology. This chip, mounted behind a stack of two microchannel plates, is used in a positive ion mass spectrometer selected by the European Space Agency for the ROSETTA cometary mission. Two functions are integrated on the chip: a dual row of 512 anodes, each having an area of 22 μm×8 mm for the collection of electrons, and two separate anode multiplexer and charge amplifier units. For redundancy reasons the chip has been designed such that the two anode rows with their associated electronics are identical and may be used independently with separate clocks and power supplies. Tests have confirmed that the LEDA512/microchannel plate combination is working properly as an ion detector and that excellent noise and response may be obtained in combination with the mass spectrometer.

A novel radiation imaging sensor based on self-activated pixels

A new position sensitive detector for charged particles and X-rays is proposed based on pixels containing MOS transistors as preamplifiers. The output of the preamplifiers is shorted to strip buses to obtain two-dimensional information with readout requirements similar to a strip detector. The total pixel capacitance is low enough (20-40 fF) to allow a large potential increase at the pixel that collected the charge. The nonlinearity introduced by the large voltage rise effectively switches on the transistors of this pixel and leaves all the other pixels of the same line at a low transconductance state, resulting in an excellent noise performance. >