Srdan Brkic

Analysis of one-step majority logic decoding under correlated data-dependent gate failures

In this paper we present analysis of one-step majority logic decoders made of unreliable components in the presence of data-dependent gate failures. Gate failures are modeled by a Markov chain, and based on the combinatorial representation of the fault configurations, a closed-form expression for the average bit error rate is derived for a regular LDPC code ensemble. Presented analysis framework is then used for obtaining upper bounds on decoding performance under timing errors.

On Fault Tolerance of the Gallager B Decoder Under Data-Dependent Gate Failures

In this letter, we characterize the effect of data-dependent gate failures on the performance of the Gallager B decoder of low-density parity-check codes. We show that this type of failures makes the decoder dependent on a transmitted codeword, thus rendering inapplicable the traditional analysis tools such as density evolution and trapping sets. By using Monte Carlo simulations, we identify two operating regions: one in which hardware unreliability leads to significant performance degradation and another in which the performance loss is negligible. Based on these results, we propose a simple modification of the decoder that ensures its fault tolerance.

Fault-resilient decoders and memories made of unreliable components

In this paper we present our recent results on iterative Gallager B decoder made of unreliable logic gates. We show evidence that probabilistic behavior of a decoder due to unreliable components can be exploited to our advantage and lead to an improved performance and reduced hardware redundancy. We provide examples of such decoder behavior and give an explanation of this phenomenon using iterative decoding dynamics. Iterative decoding can be viewed as a recursive procedure for Bethe free energy function minimization, and the randomness in a message update may help the decoder to escape from local minima. The decoder operates in a stochastic fashion, but the random perturbations do not require any additional hardware as they are built-in the faulty hardware itself.

Majority Logic Decoding Under Data-Dependent Logic Gate Failures

A majority logic decoder made of unreliable logic gates, whose failures are transient and data-dependent, is analyzed. Based on a combinatorial representation of fault configurations a closed-form expression for the average bit error rate for a one-step majority logic decoder is derived, for a regular low-density parity-check (LDPC) code ensemble and the proposed failure model. The presented analysis framework is then used to establish bounds on the one-step majority logic decoder performance under the simplified probabilistic gate-output switching model. Based on the expander property of Tanner graphs of LDPC codes, it is proven that a version of the faulty parallel bit-flipping decoder can correct a fixed fraction of channel errors in the presence of data-dependent gate failures. The results are illustrated with numerical examples of finite geometry codes.

Reliability of Memories Built From Unreliable Components Under Data-Dependent Gate Failures

In this letter, we investigate fault-tolerance of memories built from unreliable cells. In order to increase the memory reliability, information is encoded by a low-density parity-check (LDPC) code, and then stored. The memory content is updated periodically by the bit-flipping decoder, built also from unreliable logic gates, whose failures are transient and data-dependent. Based on the expander property of Tanner graph of LDPC codes, we prove that the proposed memory architecture can tolerate a fixed fraction of component failures and consequently preserve all the stored information, if code length tends to infinity.

Low complexity memory architectures based on LDPC codes: Benefits and disadvantages

In this paper we investigate the problem of information storage in inherently unreliable memory cells. In order to increase the memory reliability, information is stored in memory cells as a codeword of a low-density parity-check (LDPC) code, while the memory content is updated periodically by an error correction scheme. We first present an overview on the state-of-the memory architectures based on LDPC codes, and then asses the benefits of using the coded architectures expressed through the increased reliability. In addition, we provide upper bounds on the complexity of such memories.

Guaranteed error correction of faulty bit-flipping decoders under data-dependent gate failures

In this paper we analyze the effect of hardware unreliability to performance of bit-flipping decoders of low-density parity-check (LDPC) codes. We apply expander arguments to show that the simple parallel bit flipping decoder, built partially from faulty gates, can correct a linear fraction of worst case channel errors, when gate failures are correlated and dependent on the switching activity of logic gates. In addition, we provide a lower bound on the guaranteed error correction of LDPC codes with left degree of at least eight.

Hard-decision decoding of LDPC codes under timing errors: Overview and new results

This paper contains a survey on iterative decoders of low-density parity-check (LDPC) codes built form unreliable logic gates. We assume that hardware unreliability comes from supply voltage reduction, which causes probabilistic gate failures, called timing errors. We are able to demonstrate robustness of simple Gallager B decoder to timing errors, when applied on codes free of small trapping sets, as well as positive effects that timing errors have on the decoding of codes with contain small trapping sets. Furthermore, we show that concept of guaranteed error correction can be applied to the decoders made partially from unreliable components. In contrast to the decoding under uncorrelated gate failures, we prove that bit-flipping decoding under timing errors can achieve arbitrary low error probability. Consequently, we formulate condition sufficient that memory architecture, which employs bit-flipping decoder, preserved all stored information.

Multi-bit flipping algorithms with probabilistic gradient descent

A new class of bit flipping algorithms for low-density parity-check codes over the binary symmetric channel is proposed. The algorithms employ multiple bits at a variable node to represent its reliability, and multiple bits a check node to capture the sequence of its syndrome values. The check node update function thus requires a simple bit-shift operation, while the variable node updates require a nonlinear Boolean function. This class of multi-bit flipping (MBF) algorithms is enhanced by the probabilistic gradient descent (PGD) algorithm. The gradient descent algorithm minimizes the variable node energy function which, in addition to the classical term which quantifies the discrepancy between the variable estimate and channel value, also involves an additive term defined as a weighted sum of neighboring check node states. Only the variable nodes with the maximal value of energy are eligible for updating, but the updates are not done by default but probabilistically. The resulting probabilistic gradient descent multi-bit flipping PGD-MBF algorithm combined with rewinding improves the codeword probability of error while keeping the complexity lower than that of the state-of-the-art algorithms of comparable throughput.

Stochastic resonance in iterative decoding: Message passing and gradient descent bit flipping

This paper contains a survey on iterative decoders of low-density parity-check (LDPC) codes made of unreliable logic gates that are capable to provide lower probability of error, when compared to their perfectly reliable counterparts. We have recently shown that the error-floor performance of message-passing decoders can be improved, if randomness that exists in unreliable logic gates is incorporated into decoding deliberately, without any complexity cost. Furthermore, we have shown that controlling the level of unreliability enable us to exploit the stochastic resonance phenomenon, previously observed in theoretical physics, electronic and magnetic systems. In contrary to common belief, we have shown that for a narrow range of gate failure probability the overall decoding performance is dramatically increased. In this paper, we show that the effect of stochastic resonance is even more noticeable for the case of the gradient descent bit-flipping (GDBF) algorithm. This decoder combines the simplest iterative decoding algorithm with gradient descent optimization, making it an attractive solution for a variety of low complexity storage systems, or code-based cryptosystems. In addition, we show that getting the most of the stochastic resonance is essentially a deep learning problem, since setting the levels of unreliability for individual parts of the decoder by a training process is a step toward incorporating the machine learning techniques into design and analysis of iterative decoders of LDPC codes.