Sreela Sasi

Decimal multiplication using compact BCD multiplier

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. The basic building block of a decimal multiplier is a single digit multiplier. It accepts two Binary Coded Decimal (BCD) inputs and gives a product in the range [0, 81] represented by two BCD digits. A novel design for single digit decimal multiplication that reduces the critical path delay and area is proposed in this research. Out of the possible 256 combinations for the 8-bit input, only hundred combinations are valid BCD inputs. In the hundred valid combinations only four combinations require 4 times 4 multiplication, 64 combinations need 3 times 3 multiplication, and the remaining 32 combinations use either 3 times 4 or 4 times 3 multiplication. The proposed design makes use of this property. This design leads to more regular VLSI implementation, and does not require special registers for storing easy multiples. This is a fully parallel multiplier utilizing only combinational logic, and is extended to a Hex/Decimal multiplier that gives either a decimal output or a binary output. The accumulation of partial products generated using single digit multipliers is done by an array of multi-operand BCD adders for an (n-digit times n-digit) multiplication.

Color-Based Signal Light Tracking in Real-Time Video

Tracking or detecting the position and color of signal lights has an important role in transport industry. Auto detection of signal light colors and their position using computer vision techniques provides or acts as a proof against a fraudulent claim losses. The current technology, such as vehicle mounted recording system, provides event recognition videos and the cause behind an accident. But it does not provide the complete information about color associated with signal lights. The detection of the color of a signal light under different illuminations is a critical issue. In this research, an intelligent method for tracking color of signal lights using La*b* color model combined with contour tracking is proposed. This research finds application in transportation, law enforcement and insurance claims. The system increases the efficiency of the accident investigation process and reduces the economic loss associated with automobile accidents of all types.

A New Look at Reversible Logic Implementation of Decimal Adder

Reversibility plays a fundamental role when computations with minimal energy dissipation are considered. In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, quantum computing and nanotechnology. This research proposes a new implementation of Binary Coded Decimal (BCD) adder in reversible logic. The design reduces the number of gates and garbage outputs compared to the existing BCD adder reversible logic implementations. So, this design gives rise to an implementation with a reduced area and delay.

Performance analysis of double digit decimal multiplier on various FPGA logic families

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of [(n/2 +1] cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard.

Performance analysis of FIR digital filter design: RNS versus traditional

This paper presents performance analysis of Residue Number System (RNS) based Finite Impulse Response (FIR) digital filters and traditional FIR filters. This research is motivated by the importance of an efficient filter implementation for digital signal processing. The comparison is done in terms of speed and area requirement for various filter specifications. RNS based FIR filters operate more than three times faster and consumes only about 60% of the area than traditional fitter when number of filter taps is more than 32. The area for RNS filter is increasing at a lesser rate than that for traditional resulting in low-power consumption. RNS is a non-weighted number system without carry propagation between different residue digits. This enables simultaneous parallel processing on all the digits resulting in high speed addition and multiplication in RNS domain. Such compact and high speed real-time digital filters find applications in radar, communications and image processing systems.

Handwritten character recognition using fuzzy logic

The present paper discusses an application of fuzzy set theory to handwritten character recognition. A nonmathematical, heuristic approach to structural pattern recognition is used. Entities are given in the form of fuzzy matrix and are processed by fuzzy logic according to the membership values in different categories of features stored. A computer simulation for English alphabets, and some results are presented.

Ontology-based Sentiment Analysis Process for Social Media Content

Abstract Social media provides a platform where users share an abundance of information on anything and everything. The information may consist of users’ emotions, feedbacks, reviews, and personal experiences. In this research a novel Ontology-based Sentiment Analysis Process for Social Media content (OSAPS) with negative sentiments is presented. The social media content is automatically extracted from the twitter messages. An ontology-based process is designed to retrieve and analyse the customers’ tweet with negative sentiments. This idea is demonstrated with the identification of customer dissatisfaction of the delivery service issues of the United States Postal Service, Royal Mail of United Kingdom, and Canada post. The tweets related to the delivery service include delay in delivery, lost package/s or improper customer services at the office in person or at call centres. A combination of technologies for twitter extraction, data cleaning, subjective analysis, ontology model building, and sentiment analysis are used. The results from this analysis could be used by the company to take corrective measures for the problems as well as to generate an automated online reply for the issues. A rule-based classifier could be used for generating the automated online replies.

Biometric authentication for e-commerce transaction

E-commerce is an outcome of globalization and technology outbreak of the 21st century. The consistency on Internet privacy protection plays a major role to boost the growth of e-commerce. E-commerce industry is slowly addressing security issues on their internal networks. But security protection for the consumers is still in its infancy stage posing a barrier to the development of e-commerce. There is a growing need for a combination of legislation and technical solutions to globally secure customer privacy. The U.S Federal Trade Commission has identified the need for defining privacy policies to address consumer data security. A technology solution using biometric technique is proposed for preventing identity theft and false authentication in the course of e-commerce transactions. This research proposes a Web-based architecture that uses the encrypted iris patterns as a biometric attribute for authentication of a customer for e-commerce transactions, because iris patterns are unique to an individual.

Reversible Binary Coded Decimal Adders using Toffoli Gates

Reversibility plays a fundamental role when computations with minimal energy dissipation are considered. This research describes Toffoli Gate (TG) implementations of conventional Binary Coded Decimal (BCD) adders, adders for Quick Addition of Decimals (QAD), and carry select BCD adders suitable for multi-digit addition. For an N-digit fast adder, partial parallel processing is done on all digits in the decimal domain. Such high-speed BCD adders find application in realtime processors and internet-based computing. An analysis of delay normalized to a TG and quantum cost of BCD adders is presented. Implementations using TGs and Fredkin Gates (FRGs) are compared based on quantum cost, number of gates, garbage count and delay, and the results are tabulated.

Hazards in CMOS circuits

This paper addresses both the detection and elimination of hazards in different configurations of CMOS circuits. The analysis of hazards in combinational circuits using logic gates and their hazard-free designs have already been treated in detail in many standard text books. However, the current trend in the design of switching circuits have shifted from the mere interconnection of logic gates to more complex networks of MOS transistors. This necessitates the analysis of hazards in CMOS and pass networks, and their elimination in these networks. This paper gives the necessary and sufficient conditions for the presence of hazards in CMOS networks. The presence of hazards have been verified using SPICE simulation. Different methods of eliminating hazards in these networks are presented. In addition, new design techniques for the hazard-free design of optimal CVSL circuits are also given in this paper.