Sribalan Santhanam

A low-cost 300 MHz RISC CPU with attached media processor

This custom CPU derived from the StrongARM/sup TM/ 110 is capable of more than 2 billion 16 b operations per second (2 BOPs). Starting with the original design, an attached media processor (AMP) is integrated along with a synchronous DRAM memory controller and separate I/O bus. In addition, several enhancements are made to the CPU and cache subsystem and the chip is reduced from 0.35 /spl mu/m to 0.28 /spl mu/m technology. The chip includes 3.3M transistors and measures 60 mm/sup 2/. It dissipates less than 3 W at 300 MHz at 2.0 V internal, 3.3 V I/O. The chip supports dynamic clock frequency switching for reduced operating power during low performance demands. There are 333 separately conditioned clocks on the chip. For battery powered applications, Vdd is reduced to achieve <0.5 W operation at 150 MHz. The chip is pseudo-static and supports clock stop and IDDQ testing.

A 1 GHz power efficient single chip multiprocessor system for broadband networking applications

The Broadcom BCM12500 is a high performance system on a chip (SOC) targeted at network centric tasks. The chip consists of two high performance SB-1 MIPS64/sup TM/ CPUs, a shared 512 KB L2 cache, a DDR memory controller, and integrated I/O. All major blocks of the processor are connected together via the ZBbus/sup TM/; a high speed split transaction fully coherent multi processor bus. Three Gigabit Ethernet MACs enable a direct interface to network elements. High-speed system I/O is provided using AMDs Lightning Data Transport (LDT/sup TM/) I/O fabric and a 66 MHz PCI bus. The die measures 14.2 mm by 13.3 mm in a bulk 0.15 /spl mu/m CMOS technology and has a power dissipation of 13 W at 1.2 V and 1 GHz.