Daniel Murray

A low-cost 300 MHz RISC CPU with attached media processor

This custom CPU derived from the StrongARM/sup TM/ 110 is capable of more than 2 billion 16 b operations per second (2 BOPs). Starting with the original design, an attached media processor (AMP) is integrated along with a synchronous DRAM memory controller and separate I/O bus. In addition, several enhancements are made to the CPU and cache subsystem and the chip is reduced from 0.35 /spl mu/m to 0.28 /spl mu/m technology. The chip includes 3.3M transistors and measures 60 mm/sup 2/. It dissipates less than 3 W at 300 MHz at 2.0 V internal, 3.3 V I/O. The chip supports dynamic clock frequency switching for reduced operating power during low performance demands. There are 333 separately conditioned clocks on the chip. For battery powered applications, Vdd is reduced to achieve <0.5 W operation at 150 MHz. The chip is pseudo-static and supports clock stop and IDDQ testing.

A non-quasistatic semi-empirical model for small geometry MOSFETs☆

Abstract A new charge-oriented semi-empirical non-quasistatic (NQS) model is developed for small geometry MOSFETs that is computationally efficient to be useful for circuit simulation. The NQS model includes the effect of velocity saturation, gate field dependent mobility, charge sharing, drain induced barrier lowering and geometric dependencies of threshold voltage. To model the carrier inertia that causes non-steady state conditions, a non-quasistatic model is adopted. An approximate inversion charge profile is used to reduce the nonlinear current-continuity equation to an ordinary differential equation. The model is valid in all regions of operation (weak, moderate and strong inversion) and is derived without resorting to the approximate arbitrary channel charge partitioning. The results from the proposed model are examined and compared with 2D simulation results and good agreement is obtained for the transient source, drain and gate currents for large signals applied to the gate.