Stacy H. Gleixner

Teaching design of experiments and statistical analysis of data through laboratory experiments

A new laboratory course at San Jose State University, Advanced Thin Film Processes, integrates fabrication of thin films with design of experiment and statistical analysis of data. In the laboratory section of this course, students work through six multi-week modules that increase in the complexity of design of experiment and statistical analysis of data. The six modules have been developed with a standard format that includes learning objectives, background on the specific thin film process, theory of design of experiment principles, instructor notes, dry lab exercises, experimental plan worksheets, and assessment tools. While the modules were developed for a semiconductor processing class, they can easily be implemented in other engineering classes. The modules have been developed with a robust framework that allows the instructor to teach design of experiments and statistical analysis of data along with the specific engineering principles related to their class.

Microelectronics process engineering program at SJSU

At present, there is a need for engineers with CMOS processing knowledge, statistical process control (SPC) skills, and the ability to work in an interdisciplinary team environment and assume leadership roles. San Jose State University are developing an interdisciplinary lab-based microelectronics process engineering program that introduces SPC and DOE to students in a microelectronics manufacturing environment. At the heart of the program are three courses, each of which is imagined to be a division of a fictitious semiconductor fabrication company (Spartan Semiconductor Services, Inc., or S3i). The divisions are: Digital NMOS division (MatE/EE129: Introduction to IC Fabrication), Thin Film Research Division (MatE/ChE 166: Advanced Thin Film Processes) and CMOS Division and SPC task force (MatE/EE 167: Microelectronics Manufacturing Methods). Several unique features of the program are its introduction of SPC in a microelectronics manufacturing environment, the inclusion of design of experiments (DOE) topics, and the faculty-faculty, faculty-student and student-student interaction among the three courses (divisions). Ultimately, we are trying to provide a learning environment that will allow our students to be immediately productive in an IC production facility, to be able to communicate with IC process engineers, and to be prepared for graduate school programs.

Microelectronics Process Engineering: A Non-Traditional Approach to MS&E

Materials Science and Engineering straddles the fence between engineering and science. In order to produce more work-ready undergraduates, we offer a new interdisciplinary program to educate materials engineers with a particular emphasis on microelectronics-related manufacturing. The bachelors level curriculum in Microelectronics Process Engineering (μProE) is interdisciplinary, drawing from materials, chemical, electrical and industrial engineering programs and tied together with courses, internships and projects which integrate thin film processing with manufacturing control methods. Our graduates are prepared for entry level engineering jobs that require knowledge and experience in microelectronics-type fabrication and statistics applications in manufacturing engineering. They also go on to graduate programs in materials science and engineering. The program objectives were defined using extensive input from industry and alumni. We market our program as part of workforce development for Silicon Valley and have won significant support from local industry as well as federal sources. We plan to offer a vertical slice of workforce development, from lower division engineering and community college activities to industry short courses. We also encourage all engineering majors to take electives in our program. All our course and program development efforts rely on clearly defined learning objectives.

The Microstructure and Grain Size of Jet Electroplated Copper Films in Damascene Trench Features

The brightening additive level and dc current density of electroplating baths are two parameters that affect the gap-filling capability and the degree of impurity incorporation in electroplated copper films. Additive incorporation can inhibit grain growth during the room temperature recrystallization process and therefore affect the final grain size. This investigation explores the grain size and microstructure of dc jet-electroplated copper films in 0.35 and 0.50 μm Damascene trenches as a function of current density and brightening additive level after first receiving a high-temperature anneal. Unlike a previous study that explored these variables in blanket Cu films [J. Electrochem. Soc., 152, C101 (2005)], the results of this study suggest that current density, and to a lesser extent additive level, play a role in determining the final grain size in Damascene trenches. In 0.5 μm trench structures it was found that only higher dc current density levels produce larger cross-sectional grain sizes. In 0.35 μm trenches, however, both the current density and brightening additive level affected the final grain size. It thus appears that the level of geometrical constraint, the number of available nucleation sites, the amount of stored energy in the microstructure, and the degree of remnant additive incorporation are factors that could influence the final grain size.

Studying the Etch Rates and Selectivity of SiO2 and Al in BHF Solutions

One limitation to fabricating MEMS devices in some academic labs is the lack of polysilicon deposition technology. This limits the devices that can be fabricated because polysilicon is a common structural material in MEMS devices. In order to enhance the MEMS fabrication capabilities, expanding the use of Al as a structural layer has been researched. The main difficulty is the lack of a selective wet etch between the Al structural layer and the SiO2 sacrificial layer. In this study, seven etching solutions were studied on SiO2 and Al for their etch rates and selectivity. Two were buffered hydrofluoric acid (BHF) solutions with different concentrations of NH4F. Four were BHF solutions with propylene glycol or glycerin at different concentrations. The seventh solution was a commercial solution, Pad Etch 4. Among the seven etching solutions, 5:1 BHF gave the best selectivity between SiO2 and Al. Increasing the NH4F concentration from 5 to 7 parts did not increase the selectivity, but selectivity increased by adding NH4F in HF solution. Adding propylene glycol or glycerin to the 7:1 BHF solution did not increase the selectivity. When glycerin was added to 7:1 BHF solution it provided superior selectivity than was obtained from adding propylene glycol to 7:1 BHF. This paper will present the etch rates and selectivity of the 7 solutions along with comparisons with other published results.

The Trials and Errors of Collaborative Learning: A New Faculty Perspective

There are a number of teaching techniques that have proven very useful in involving the students and increasing their learning. As a new faculty member, I have chosen to improve my teaching by first implementing collaborative learning exercises into my classes. The exercises I have used include in-class group problem solving, informal study groups, and group term projects. In this paper, I will detail the published benefits of collaborative learning that led me to use this in my classes. The introduction of collaborative learning exercises into my lectures has also brought a number of problems and fears including time constraints, the practical issues of forming groups in large classes, and the barrier students have towards working together. From the perspective of a new faculty, I will discuss the problems I have had implementing collaborative work into my classes and tips for avoiding and overcoming the problems I have encountered.

Progress on crystalline silicon thin film solar cells by FBR-CVD: Effect of substrates and reactor design

Thin film polycrystalline solar cells on low cost substrates offer an attractive path to large scale production of solar cells with the potential to generate electricity at 1

Chromium Transport by Solid State Diffusion on Solid Oxide Fuel Cell Cathode

/W. SRI International has a propriety technology to deposit Si films in a reactor based on fluidized bed technology. The results presented in this paper show that, with a proper reactor design, Si films can be grown at rates of 7 μm/min and higher. Films are crystalline, with crystallite sizes higher than 20 μm. We have also evaluated the performance of SiO2 diffusion barriers as a potential way towards the use of low cost substrates, such as metallurgical grade Si. Whereas SiO2 layers of 0.1 μm are not sufficient to stop P diffusion from the substrate to the film, 0.7 μm layers are thick enough to accomplish this goal. The reactor configuration can be used for continuous and integrated cell/panel fabrication. At present we are building a first continuous reactor, and in this paper we present some preliminary considerations.