Stacy J. Garvin

A uniform bandwidth PLL using a continuously tunable single-input dual-path LC VCO for 5Gb/s PCI express Gen2 application

A 4.75 to 6.1 GHz PLL with uniform bandwidth control is implemented in 90 nm CMOS. Utilizing a continuously tunable single-input dual-path LC VCO and a constant-gain phase detector, the proposed architecture is well suited to implementing PLLs that must be compliant with standards that specify minimum and maximum allowable PLL bandwidths such as PCI Express Gcn2 or FB-DIMM applications. This work also addresses noise and coupling aspects in dual-path VCO design. The measurement results show that the PLL bandwidth and random jitter (R.I) variations are well regulated and that the use of a differentially controlled dual-path VCO is important for deterministic jitter (DJ) performance.

A Continuously Tunable LC-VCO PLL with Bandwidth Linearization Techniques for PCI Express Gen2 Applications

This paper describes bandwidth linearization techniques in phase-locked loop (PLL) design for common-clock serial link applications. Utilizing a continuously tunable single-input dual-path LC VCO and a constant-gain phase detector, a proposed architecture is well suited to implementing PLLs that must be compliant with standards that specify minimum and maximum allowable bandwidths such as PCI Express Gen2 or FB-DIMM applications. A prototype 4.75 to 6.1-㎓ PLL is implemented in 90-nm CMOS. Measurement results show that the PLL bandwidth and random jitter (RJ) variations are well regulated and that the use of a differentially controlled dualpath VCO is important for deterministic jitter (DJ) performance.