Stanley C. Keeney

DSP core with parallel module testability

A description is given of a custom-designed, 160 K-transistor TMS320C25 DSP (digital signal processor) core processor, which has been combined with a 5 K user-programmable gate array and built-in parallel module testability. The research vehicle, designed to analyze practical issues of embedded core DSPs and manufactured in a 1- mu m CMOS process, runs at a 50-MHz clock frequency in the DSP core and has a gate delay of 0.5 ns (FO=3) in the gate array. The parallel module test (PMT) methodology is used to obtain and effectively test the DSP core during manufacturing. The method introduces a minimum speed penalty, approximately one quarter of a nanosecond, under normal operation paths and requires only one dedicated TEST pin at the device package. The joint test action group PMT system architecture can also support board-level testing.<<ETX>>