Stanley L. Chen

Design and verification of Distributed RAM using Look-Up Tables in an SOI-based FPGA

A novel architecture of the configurable Distributed Random Access Memory (RAM) logic based on Look-Up Tables (LUTs) in the Logic Block (LB) is proposed and implemented in a tile-based FPGA manufactured with a 0.5µm SOI-CMOS logic process. The Distributed RAM can be configured in two modes: Single-Port RAM and Dual-Port RAM. Due to its resource abundance and low latency the Distributed RAM can complement Block RAM in implementing the data storage logic of many applications. The functionality and performance of the Distributed RAM have been proven in our test circuit. Comparing with the published data on the Distributed RAM in Xilinx Spartan FPGA, our Distributed RAM average access time has about 21% improvement.

The design methodology of a High-Performance dataflow supercomputer on a reconfigurable chipset for use in 3D graphics applications

The dataflow supercomputer outperforms the conventional multi-core supercomputers based on CPU/ GPUs in compute-intensive exascale High Performance Computing (HPC) applications by orders of magnitude in terms of computing and power performance [1]. The best performance has been reported by application-specific heterogeneous dataflow supercomputers built on commercial FPGAs with a speedup over 200× compared to a single-core computer [2]. As an HPC application, a 3D graphics application for massively complex models is in an urgent need of high-performance computing and low power consumption. In this paper, an innovative chipset-on-card design methodology for 3D supercomputing applications based on K-dimensional binary space partitioning (BSP) out-of-core ray-tracing algorithm [3] is described for achieving a performance higher than the reported dataflow supercomputers. This algorithm is reformulated as a set of parallel pipelines with minimal data exchange and partitioned into separate data flows. The entire data flow diagram is then mapped into a reconfigurable high-performance computing chipset-on-card.

Mapper design for an SOI-based FPGA

This paper addresses the design of the mapping tool used for the FPGA application implementation in our SRAM-based FPGAs fabricated in a 0.5 micron SOI-CMOS process. Comparing with the existing mapping tools from academia, we propose several techniques of packing and clustering to improve the technology mapping. The proposed algorithms provide a closer matching of the user logic netlist with the underlining FPGA architectural features and thus improve on the cluster occupancy of the logic resources. The result is proven in extensive test circuits used in our FPGA design. MCNC testbench comparison result is presented.

Automated test bitstream generation for an SOI-based FPGA

In this paper, we propose a methodology of the automated bitstream generation for conducting high-testability FPGA tests. In order to study the efficiency of our solution we will explore our methodology in the test of an SOI-based FPGA. We use a semi-automated approach of the bitstream generation for ease of test vector design with high functionality and fault coverage. The methodology from this research is extensively exercised in the design process. The quality of this methodology is proven by the efficiency of the test vector suite used in the wafer and packaged tests. The same approach can also be used in the bitstream generation for FPGA application.

The Design and Verification of FPGA CAD Toolset

This paper introduces a complete CAD toolset for the implementation of digital logic in a field-programmable gate array (FPGA) platform. Compared with existing academic toolsets, this toolset introduces formal verification in each step of the tool flow, especially the formal verification of the configuration bitstream. The FPGA CAD tool verification flow using Formality is presented in detail. Using plug-in technology, we have developed an integrated FPGA design kit to incorporate all tools together.

Design and Implementation of a Novel Boundary-Scan Circuit in FPGA’s Chip

This chapter presents a novel Boundary-Scan circuit compatible with IEEE1149.1 standard in a field-programmable gate array (FPGA). The novel Boundary-Scan circuit not only facilitates the chip test as well as an assembled printed circuit board (PCB) test but also severs as the configuration and verification of FPGA. This circuit is designed based on the configurable feature of FPGA. In this design, the boundary-scan chain can be configured to any desired length, which can efficiently improve the effective test speed. Also, a configurable scan chain controlled by the novel Boundary-Scan circuit can be flexibly formed in the FPGA core from which the controllability and observability of internal signals in the FPGA core are largely enhanced but not increase the overhead design. Besides, the conventional INTEST of Joint Test Action Group (JTAG) can be extended from single-step logic to multiple-step logic by connecting JTAG test clk input (TCK) signal into the test logic of FPGA core. The novel Boundary-Scan circuit has been implemented in an static random access memory (SRAM) based FPGA fabricated by a 0.5 µm silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The test results from the fabricated chip indicate that this circuit successfully realizes the desired functions in programming, verification, and testing.

Design and verification of logic block circuit in an SOI-based FPGA

A novel logic block circuit consisting of two multi-mode logic cells is proposed for the design of a tile-based FPGA fabricated with a 0.5µm SOI-CMOS logic process. Each logic cell contains two 3-LUTs. The proposed 3-LUT based logic cell circuit increases logic density by about 12% compared with a traditional 4-LUT implementation. The logic block can be used in two functional modes: LUT mode and Distributed RAM mode, the latter of which can be configured in two modes: Single-Port RAM and Dual-Port RAM. Comparing with the published data on the CLB in Xilinx Spartan FPGA, the maximum LUT logic propagation delay has about 20% improvement and the Distributed RAM average access time has about 21% improvement.

Design and implementation of a novel Boundary-Scan circuit in an SOI-Based FPGA

A novel Boundary-Scan circuit compatible with IEEE 1149.1 standard and designed for our SOI-Based FPGA is presented in this paper. The new Boundary-Scan circuit serves the test of FPGA at the chip as well as board level and the added features facilitate the configuration and verification functions of FPGA. The Boundary-Scan circuit in this paper has been implemented in an SRAM-Based FPGA fabricated by a 0.5µm SOI-CMOS process. The test results from the fabricated chip demonstrate that this circuit successfully realizes the desired functions in programming, verification and testing.

Design and verification of the programming circuit in an application-specific FPGA

In this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific FPGAs that share a common architecture. Each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. The parametrized design methodology is presented here to achieve this goal. Even though our focus is on the programming circuitry that provides the interface between the FPGA core circuit and the external programming hardware, the parametrized design method can be generalized to the design of entire chip for all members in the FPGA family. The method presented here covers the generation of the design RTL files and the support files for synthesis, place-and-route layout and simulations. The proposed method is proven to work smoothly within the complete chip design methodology. We will describe the implementation of this method to the design of the programming circuit in details including the design flow from the behavioral-level design to the final layout as well as the verification. Different package options and different programming modes are included in the description of the design. The circuit design implementation is based on SMIC 0.13-micron CMOS technology.

A synthesis tool for a tile-based heterogeneous FPGA

A multi-mode logic cell architecture in a tile-based heterogeneous FPGA is proposed, and a logic synthesis tool, called Vsyn, based on this architecture is presented. The logic cell architecture design and its synthesis tool development are strongly influencing each other. Any feature or parameter from one needs to be fully exercised and verified on the other. In this paper, we presented experimental results based MCNC benchmarks to show that the integration of the synthesis tool and the FPGA architecture can achieve high performance in the targeted FPGA applications. In addition, Vsyn can also target embedded special-purpose macros for the heterogeneous FPGA.