Zhongli Liu

A silicon capacitive microphone based on oxidized porous silicon sacrificial technology

A new capacitive microphone fabrication technology is proposed. It uses oxidized porous silicon sacrificial technology to make air gaps and using KOH etching technique to make the backplate containing acoustic holes based on the principle that the heavily p/sup +/-doped silicon can be nearly etched in KOH solution. The innovation of the method is using oxidized porous silicon technology. The sensitivity of the fabricated microphone is from -55 dB (1.78 mV/Pa) to -45 dB (5.6 mV/Pa) in the frequency range of 500 Hz to 25 kHz. Its cut-off frequency is higher than 20 kHz.

A radiation-hardened SOI-based FPGA

A radiation-hardened SRAM-based field programmable gate array VS1000 is designed and fabricated with a 0.5 m partial-depletion silicon-on-insulator logic process at the CETC 58th Institute. The new logic cell (LC), with a multi-mode based on 3-input look-up-table (LUT), increases logic density about 12% compared to a traditional 4-input LUT. The logic block (LB), consisting of 2 LCs, can be used in two functional modes: LUT mode and distributed read access memory mode. The hierarchical routing channel block and switch block can significantly improve the flexibility and routability of the routing resource. The VS1000 uses a CQFP208 package and contains 392 reconfigurable LCs, 112 reconfigurable user I/Os and IEEE 1149.1 compatible with boundary- scan logic for testing and programming. The function test results indicate that the hardware and software cooperate successfully and the VS1000 works correctly. Moreover, the radiation test results indicate that the VS1000 chip has total dose tolerance of 100 krad(Si), a dose rate survivability of 1.5 10 11 rad(Si)/s and a neutron fluence immunity of 1 10 14 n/cm 2 .

Improvement of the radiation hardness of SIMOX buried layers using nitrogen implantation

An investigation of hardening the buried oxides (BOX) in separation by implanted oxygen (SIMOX) silicon-on-insulator (SOI) wafers to total-dose irradiation has been made by implanting nitrogen into the BOX layers with a constant dose at different implantation energies. The total-dose radiation hardness of the BOX layers is characterized by the high frequency capacitance–voltage (C–V) technique. The experimental results show that the implantation of nitrogen into the BOX layers can increase the BOX hardness to total-dose irradiation. Particularly, the implantation energy of nitrogen ions plays an important role in improving the radiation hardness of the BOX layers. The optimized implantation energy being used for a nitrogen dose, the hardness of BOX can be considerably improved. In addition, the C–V results show that there are differences between the BOX capacitances due to the different nitrogen implantation energies.

DSOI FET - A novel TID tolerant SOI transistor

Charge trapping in the buried oxide can lead to serious back-channel leakage and make SOI (Silicon-on-Insulator) transistors more sensitive to total dose radiation. In this paper, a new DSOI (Double SOI) transistor is proposed, which utilizes the method of back-gate biasing to force an external electric field, and then depress the back channel formation during total dose irradiation. The simulation and testing results both indicate that, for a given structure, when a -3V bias is applied to the back-gate, the DSOI transistor can tolerant a total dose radiation of 500k rad(Si). This methodology fits all kinds of SOI MOSFETs, especially for the Fully-Depletion SOI transistors. With commercial (not especially hardened) buried oxide, DSOI device can have better radiation hardening performance than its both companions - FDSOI and PDSOI transistors.

A 14-bit wide temperature range differential SAR ADC with an on-chip multi-segment BGR

A 14-bit low power self-timed differential successive approximation (SAR) ADC with an on-chip multi-segment bandgap reference (BGR) is described. An on-chip multi-segment BGR, which has a temperature coefficient of 1.3 ppm/°C and a thermal drift of about 100 μV over the temperature range of −40 to 120 °C is implemented to provide a high precision reference voltage for the SAR ADC. The Gray code form is utilized instead of binary form mode control to reduce substrate noise and enhance the linearity of the whole system. Self-timed bit-cycling is adopted to enhance the time efficiency. The 14-bit ADC was fabricated in a TSMC 0.13 μm CMOS process. With the on-chip BGR, the SAR ADC achieves an SNDR of 81.2 dB (13.2 ENOB) and an SFDR of 85.2 dB with a conversion rate of 2 MS/s at room temperature and can keep an ENOB of more than 12 bits at a conversion rate of 2 MS/s over the temperature range from −40 to 120 °C.

Influence of fluorine on radiation-induced charge trapping in the SIMOX buried oxides

Charge trapping in the fluorinated SIMOX buried oxides before and after ionizing radiation has been investigated by means of C-V characteristics. Radiation-induced positive charge trapping which results in negative shift of C-V curves can be restrained by implanting fluorine ions into the SIMOX buried oxides. Pre-radiation charge trapping is suppressed in the fluorinated buried oxides. The fluorine dose and post-implantation anneal time play a very important role in the control of charge trapping.

A low power and radiation-tolerant FPGA implemented in FD SOI process

A 330,000 gate field programmable gate array (FPGA) VS12C fabricated on 0.2μm full-depletion silicon-on-insulator (FD SOI) process is presented and the test results indicate this chip has the lower power and higher tolerance to radiation compared with Xilinx radiation-hardened XQVR300 chip implemented on 0.22μm epitaxial silicon. This paper demonstrates the benefit of the FD SOI technology on low power and radiation-tolerant FPGA circuit design.

Design and implementation of a programming circuit in radiation-hardened FPGA

We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 × 105 rad(Si), dose rate survivability of 1.5 × 1011 rad(Si)/s and neutron fluence immunity of 1 × 1014 n/cm2.

The Design and Verification of FPGA CAD Toolset

This paper introduces a complete CAD toolset for the implementation of digital logic in a field-programmable gate array (FPGA) platform. Compared with existing academic toolsets, this toolset introduces formal verification in each step of the tool flow, especially the formal verification of the configuration bitstream. The FPGA CAD tool verification flow using Formality is presented in detail. Using plug-in technology, we have developed an integrated FPGA design kit to incorporate all tools together.

Ionizing Irradiation Effect of Fluorine Implanted Metal-BOX-Silicon Structure Based on SOI

Ionizing irradiation effects on MBS (metal-BOX-silicon) have been studied in this paper. Through pre- and post-irradiation high-frequency (HF) C-V curves of MBS of several samples in which fluorine was implanted into BOX of SIMOX, it was found that PD fluoridated SIMOX is beneficial to harden buried oxide layer