Stefan Schippers

A 65 nm 1 Gb 2b/cell NOR Flash With 2.25 MB/s Program Throughput and 400 MB/s DDR Interface

This paper describes a 1.8 V, 1 Gb 2 b/cell NOR flash memory, based on time-domain voltage-ramp reading concept and designed in a 65 nm technology. Program method, architecture and algorithm to reach 2.25 MB/s programming throughput are also presented, as well as the read concept, allowing 70 ns random access time and a 400 MB/s sustained read throughput via a DDR interface.

A 65nm 1Gb 2b/Cell NOR Flash with 2.25MB/s Program Throughput and 400MB/s DDR interface

This paper describes a 1.8 V, 1 Gb 2 b/cell NOR flash memory, based on time-domain voltage-ramp reading concept and designed in a 65 nm technology. Program method, architecture and algorithm to reach 2.25 MB/s programming throughput are also presented, as well as the read concept, allowing 70 ns random access time and a 400 MB/s sustained read throughput via a DDR interface.

A 20 MB/s data rate 2.5 V flash memory with current-controlled field erasing for 1 M cycle endurance

Techniques to improve endurance and access time are applied to 2.5V high-density flash memory. A 4Mb flash product is used as a test vehicle for an erase method that extends the program/erase (P/E) endurance beyond 106 cycles. An embedded /spl mu/ROM controller with optimized algorithms (zero P/E array stress) minimizes erase time (parallel sector erase) and reduces testing time (BIST techniques). A 20MB/s read data throughput at 2.5V is obtained in OE synchronized data transfer mode. Dynamic redundancy enhances repair capability.