Stefan Scholl

Efficient Maximum-Likelihood Decoding of Linear Block Codes on Binary Memoryless Channels

In this work, we consider efficient maximum-likelihood decoding of linear block codes for small-to-moderate block lengths. The presented approach is a branch-and-bound algorithm using the cutting-plane approach of Zhang and Siegel (IEEE Trans. Inf. Theory, 2012) for obtaining lower bounds. We have compared our proposed algorithm to the state-of-the-art commercial integer program solver CPLEX, and for all considered codes our approach is faster for both low and high signal-to-noise ratios. For instance, for the benchmark (155, 64) Tanner code our algorithm is more than 11 times as fast as CPLEX for an SNR of 1.0 dB on the additive white Gaussian noise channel. By a small modification, our algorithm can be used to calculate the minimum distance, which we have again verified to be much faster than using the CPLEX solver.

Challenges and Limitations for Very High Throughput Decoder Architectures for Soft-Decoding

In modern communications systems the required data rates are continuously increasing. Especially consumer electronic applications like video on demand, IP-TV, or video chat require large amounts of bandwidth. Already today’s applications require throughputs in the order of Gigabits per second and very short latency. Current mobile communications systems achieve 1 Gbit/s (LTE [1]) and wired transmission enables even higher data rates of 10 Gbit/s (e.g., Thunderbolt [2], Infiniband [3]) up to 100 Gbit/s. For the future it is clearly expected that even higher data rates become necessary. Early results show throughputs in the order of 100 Tbit/s [4] for optical fiber transmissions.

Hardware implementation of a Reed-Solomon soft decoder based on information set decoding

Soft decision decoding of Reed-Solomon codes can largely improve frame errors rates over currently used hard decision decoding. In this paper, we present a new hardware implementation for soft decoding of Reed-Solomon codes based on information set decoding. To our best knowledge this is the first hardware implementation of information set decoding for long Reed-Solomon codes. We propose a reduced complexity version of the decoding algorithm, that is optimized for efficient hardware implementation and enables high throughput. The decoder was implemented on a Virtex 7 FPGA, achieving a gain of 0.75 dB compared to conventional hard decision decoding and a throughput of up to 1.19 GBit/s for the widely used RS(255,239). This gain in FER is achieved with less complexity and more than 15x larger throughput than other state-of-the-art architectures.

Hardware implementations of Gaussian elimination over GF(2) for channel decoding algorithms

In this paper, we investigate hardware implementations for Gaussian elimination of binary matrices. Gaussian elimination over GF(2) is a key operation used in several new channel decoding algorithms, that can provide large improvement of frame error rate over currently used algorithms. We first apply state-of-the-art architectures for binary Gaussian elimination to decoding algorithms. Then, we present a new hardware architecture, that has considerably less resource utilization and a higher throughput than state-of-the-art solutions. The designs have been implemented and compared on a Virtex 7 FPGA.

ML vs. BP decoding of binary and non-binary LDPC codes

It has been shown that non-binary LDPC codes have a better error correction performance than binary codes for short block lengths. However, this advantage was up to now only shown under belief propagation decoding. To gain new insights, we investigate binary and non-binary codes under ML decoding. Our analysis includes different modulation schemes and decoding algorithms. For ML decoding under different modulation schemes a flexible integer programming formulation is presented. In this paper, we show that with respect to ML decoding short non-binary LDPC codes are not necessarily superior to binary codes. The decoding gain observed under BP decoding originates mainly in the more powerful non-binary decoding algorithm.

Advanced iterative channel coding schemes: When Shannon meets Moore

The continuous demands on increased spectral efficiency, higher throughput, lower latency and lower energy in communication systems imposes large challenges on appropriate channel coding schemes and their efficient hardware implementation. Consequently, channel coding is not only a matter of information theory but also more and more knowledge on efficient parallel hardware architectures and underlying semiconductor technology is required. Finally, a deep understanding of the strong interrelation of code structure, decoding algorithms, communications performance and efficient implementation in state-of-the-art semiconductor technology is mandatory. In this paper, we will highlight this strong interrelation on some advanced iterative channel coding techniques, i.e. turbo codes and LDPC codes and demonstrate challenges and limitations with respect to throughput and latency.

A simplex algorithm for LP decoding hardware

An efficient LP decoder is the key building block for a maximum likelihood decoder based on integer programming. In this paper we propose to employ a variant of the simplex algorithm for LP decoding, called the dual simplex algorithm. This algorithm has two advantages: It inherently uses the received LLRs to generate a close to optimum starting solution and it allows to reuse former LP solutions if an adaptive LP decoding scheme is used. It is shown, that the dual simplex algorithm outperforms the standard (primal) simplex by a factor of 15-20 in runtime. This allows for efficient future hardware implementations. Furthermore the use of fixed-point instead of floating-point numbers is investigated to further reduce hardware complexity.

Efficient architectures for parity check matrix generation

New advanced decoding algorithms for error correction systems can improve the frame error rate over commonly used systems. However, they also pose new challenges for their hardware implementations. One part, which consumes a considerable amount of hardware resources, is the storage of the parity check matrix. This problem has not been addressed in literature since it is not yet required by todays typically applied decoding algorithms. In this paper we investigate sophisticated hardware architectures for storing and generating parity check matrices of BCH, Reed-Solomon and LDPC codes, that exploit the matrix structures. It is shown that these new architectures largely simplify the hardware and require up to five times less area compared to state-of-the-art implementations.

A new LDPC decoder hardware implementation with improved error rates

LDPC codes are commonly decoded by conventional belief propagation algorithms like the min-sum algorithm. However especially for small block lengths belief propagation performs poorly in comparison to maximum likelihood decoding. In this paper we propose a new decoding algorithm, that is inspired by augmented belief propagation from literature and present hardware architectures and implementations for 28nm ASIC technology. The new decoder has a much higher complexity, but provides a gain of up to 1.2 dB signal-to-noise ratio compared to conventional belief propagation decoding.

Advanced hardware architecture for soft decoding Reed-Solomon codes

Soft decision decoding of Reed-Solomon codes improves decoding performance considerably in comparison to hard decision decoding. In this paper, we propose an advanced architecture based on information set decoding for processing soft information. The architecture features efficient order-2 reprocessing and handling of multiple information sets. Complexity and performance of the architecture for the widely used RS(255,239) are evaluated on a Virtex 5 FPGA. A communications gain of 1.3 dB is achieved, which outperforms to our best knowledge all other state-of-the-art implementations by more than 0.5 dB.