Stefano Brenna

A Sub-400-nT/

This paper presents a novel z-axis Lorentz force magnetometer coupled with a low-power readout integrated circuit. The sensor is fabricated using an industrial process, and exploits an Al-on-polysilicon multi-loop architecture that gives a five-fold sensitivity and resolution improvement, useful for off-resonance operation. The integrated readout is based on a differential charge amplifier front-end, and designed to be balanced with the sensor in terms of noise and power consumption. The overall system, including demodulation and filtering stages, shows a programmable full-scale up to ±2.4 mT, limited by the electronics saturation. The bandwidth can be programmed up to 150 Hz for off-resonance operation where a sub-400-nT/√Hz resolution at 775-μW power consumption is obtained, including the integrated readout and the Lorentz current. Perspectives on low-consumption driving oscillators for off-resonance mode are finally given.

\sqrt {\text {Hz}}

This brief presents a 64-channel neural recording system-on-chip (SoC) with a 20-Mb/s wireless telemetry. Each channel of the analog front end consists of a low-noise bandpass amplifier, featuring a noise efficiency factor of 3.11 with an input-referred noise of 5.6 μVrms in a 0.001- to 10-kHz band and a 31.25-kSps 6-fJ/conversion-step 10-bit SAR analog-to-digital converter. The recorded signals are multiplexed in the digital domain and transmitted via an 11.7% efficiency pulse-position modulation ultrawideband transmitter, reaching a transmission range in excess of 7.5 m. The chip has been fabricated in a 130-nm CMOS process, measures 25 mm2, and dissipates 965 μW from a 0.5-V supply. This SoC features the lowest power per channel (15 μW) and the lowest energy per bit (48.2 pJ) among state-of-the-art wireless neural recording systems with a number of channels larger than 32. The proposed circuit is able to transmit the raw neural signal in a large bandwidth (up to 10 kHz) without performing any data compression or losing vital information, such as local field potentials.

, 775-

The optimal design of SAR ADCs requires the accurate estimate of nonlinearity and parasitic effects in the feedback charge-redistribution DAC. Since the effects of both mismatch and stray capacitances depend on the specific array topology, complex calculations, custom modeling and heavy simulations in common circuit design environments are often required. This paper presents a MATLAB-based numerical tool (CSAtool) to assist the design of the charge redistribution DACs adopted in SAR ADCs. The tool performs both parametric and statistical simulations taking into account capacitive mismatch and parasitic capacitances thus computing both differential and integral nonlinearity (DNL, INL). SNDR and ENoB degradation due to static non-linear effects is also estimated. An excellent agreement is obtained with the results of circuit simulators (e.g. Cadence Spectre) featuring up to 104 shorter simulation time, allowing a large number statistical simulations which would be otherwise impracticable. Measurements on two fabricated SAR ADCs confirm that the proposed tool can be used as a valid instrument to assist the design of a charge redistribution SAR ADC and predict its static and dynamic metrics.

\mu \text{W}

The conventional binary weighted array SAR ADC is the common topology adopted to achieve high efficiency conversion, i.e. with less than 10 fJ/conversion-step, even requiring extra effort to design and simulate full custom sub-fF capacitors. This paper presents the design and the optimization of an asynchronous SAR ADC with attenuation capacitor achieving an efficiency similar to conventional binary weighted array converters but adopting standard MiM capacitors. A monotonic switching algorithm further reduces the capacitive array consumption while an asynchronous and fully-differential dynamic logic minimizes the digital power consumption. A 10-bit prototype has been fabricated in a 0.13-μm CMOS technology. At 0.5-V supply and 200-kSps sampling frequency, the ADC achieves a SNDR of 52.6 dB, an ENOB of 8.45, and a power consumption of 420 nW, corresponding to a figure-of-merit (FOM) of 6 fJ/conversion-step. This efficiency is comparable to the best results published so far and its the lowest among ADCs in 130-nm or less scaled technology. The ADC core occupies an area of only 0.045 mm2.

, Multi-Loop MEMS Magnetometer With Integrated Readout Electronics

The optimal design of SAR ADCs requires the accurate estimate of nonlinearity and parasitic effects in the feedback charge-redistribution DAC. Since the effects of both mismatch and stray capacitances depend on the specific array topology, complex calculations, custom modeling and heavy simulations in common circuit design environments are often required. This paper presents a novel MATLAB-based numerical tool to assist the design of classic, split and with attenuation capacitor binary weighted capacitive array topologies with an even number of bits from 6 to 14. The tool allows to perform both parametric and statistical simulations taking into account capacitive mismatch and parasitic capacitances in order to compute both differential- (DNL) and integral nonlinearity (INL). SNDR and ENoB degradation due to static non-linear effects is also estimated. An excellent agreement with the results obtained by the available circuit simulators (e.g. Cadence Spectre) is shown but featuring up to 104 shorter simulation time.

A 64-Channel 965-

The optimal design of SAR ADCs requires the accurate estimate of nonlinearity and parasitic capacitance effects in the feedback charge redistribution DAC. Since both contributions depend on the specific array topology, complex calculations, custom modeling and heavy simulations in common circuit design environments are often required. This paper presents a MATLAB-based numerical environment to assist the design of the charge redistribution DACs adopted in SAR ADCs. The tool performs both parametric and statistical simulations taking into account capacitive mismatch and parasitic capacitances computing both differential and integral nonlinearity (DNL, INL). An excellent agreement is obtained with the results of circuit simulators (e.g. Cadence Spectre) featuring up to 104 shorter simulation time, allowing statistical simulations that would be otherwise impracticable. The switching energy and SNDR degradation due to static nonlinear effects are also estimated. Simulations and measurements on three designed and two fabricated prototypes confirm that the proposed tool can be used as a valid instrument to assist the design of a charge redistribution SAR ADC and to predict its static and dynamic metrics. HighlightsA MATLAB-based tool for the design of capacitive array of SAR ADCs is proposed.A graphic user interface eases the handling of the implemented models.The tool results show an excellent agreement with the post-layout simulations.

\mu\text{W}

This work aims at estimating and comparing the power limits of ΔΣ and charge-redistribution successive-approximation register (CR-SAR) analog-to-digital converters (ADCs), in order to identify which topology is the most power-efficient for a target resolution. A power consumption model for mismatch-limited SAR ADCs and for discrete-time (DT) ΔΣ modulators is presented and validated against experimental data. SAR ADCs are found to be the best choice for low-to-medium resolutions, up to roughly 80 dB of dynamic range (DR). At high resolutions, on the other hand, ΔΣ modulators become more power-efficient. This is due to the intrinsic robustness of the ΔΣ modulation principle against circuit imperfections and non-idealities. Furthermore, a comparison of the area occupation of such topologies reveals that, at high resolutions and for a given dynamic range, ΔΣ ADCs result more area-efficient as well.

Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS

This paper shows, for the first time, a complete magnetic field sensing system including a Lorentz-force sensor operating out of resonance coupled to an integrated circuit for sensing and actuating the device. Working out of resonance, the trade-off between maximum sensing bandwidth and minimum detectable magnetic field is overwhelmed, improving the resolution and enlarging the bandwidth. However, the reduction of signal amplitude makes the readout electronics a critical block. Measurements carried-out on the whole system show an achievable resolution of 180 nT·mA/√Hz over a 150-Hz bandwidth and an overall power consumption of 460 μW. The integrated readout circuit low-noise performance does not limit the resolution, which is set by the MEMS thermomechanical noise.

A tool for the assisted design of charge redistribution SAR ADCs

The optimal design of successive approximation register (SAR) analog-to-digital converters (ADCs) requires the accurate estimate of nonlinearity and parasitic capacitance effects in the feedback charge-redistribution digital-to-analog converters (DACs). Since the effects of both mismatch and stray capacitances depend on the specific array topology, complex calculations, custom modeling and heavy simulations in common circuit design environments are often required. This paper presents a novel MATLAB-based numerical tool to assist the design of classic, split and with attenuation capacitor binary weighted capacitive array topologies with an even number of bits from 6 to 14. The tool allows to perform both parametric and statistical simulations taking into account capacitive mismatch and parasitic capacitances in order to compute both differential- (DNL) and integral nonlinearity (INL). Signal-to-noise plus distortion ratio (SNDR) and Effective Number of Bits (ENoB) degradation due to static non-linear effects is also estimated. An excellent agreement with the results obtained by the available circuit simulators (e.g. Cadence Spectre) is shown but featuring up to 10^4-times shorter simulation time.